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CDM ESD protection is a major ESD protection design challenge for advanced ICs, often suffering from random design failures. It was recently reported that the traditional pad-based CDM ESD protection method is fundamentally faulty, contributing to design uncertainties in CDM ESD testing and field failures. This paper reports a novel internally distributed CDM ESD protection method to overcome this major design challenge, which was validated using an internal-CDM-protected oscillator IC implemented in a foundry 45nm SOI CMOS technology. ESD protection is required for all systems.
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ESD Protection Designs: Topical Overview and Perspective
Abstract: As the ever increasing demands for performance of integrated circuit (IC) chip continue to increase, while technology scaling driven by Moore’s Law is becoming extremely challenging if not impractical or impossible, heterogeneous integration (HI) emerges as an attractive pathway to further enhance performance of Si-based CMOS chips. The underlying basis for using HI tech-nologies and structures is that IC performance goes well beyond classic logic functions; rather, functionalities and complexity of smart chips span across the full information chain, including signal sensing, conditioning, processing, storage, computing, communication, control and actua-tion, which are required to facilitate comprehensive human-world interactions. Therefore, HI technologies can bring in more function diversifications to make system chips smarter within ac-ceptable design constraints including costs. Over the past two decades or so, a large number of HI technologies have been explored to increase heterogeneities in materials, technologies, devices, circuits and system architectures, making it practically impossible to provide one single compre-hensive review of everything in the field in one paper. This article chooses to offer a topical over-view of selected HI structures that have been validated in CMOS platform, including a stacked-via vertical magnetic-cored inductor structure in CMOS, a metal wall structure in the backend of line (BEOL) of CMOS to suppress global flying noises, an above-IC graphene NEMS switch and a nano crossbar array electrostatic discharge (ESD) protection structure, and graphene ESD interconnects
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- Award ID(s):
- 1838702
- PAR ID:
- 10366268
- Date Published:
- Journal Name:
- Nanomaterials
- ISSN:
- 2079-4991
- Page Range / eLocation ID:
- 1-21
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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