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1. Reliability Improvement and Effective Switching Layer Model of Thin‐Film MoS ₂ Memristors

   https://doi.org/10.1002/adfm.202214250  

   Huang, Yifu; Gu, Yuqian; Mohan, Sivasakthya; Dolocan, Andrei; Ignacio, Nicholas_D; Kutagulla, Shanmukh; Matthews, Kevin; Londoño‐Calderon, Alejandra; Chang, Yao‐Feng; Chen, Ying‐Chen; et al (April 2023, Advanced Functional Materials)

   Abstract 2D memristors have demonstrated attractive resistive switching characteristics recently but also suffer from the reliability issue, which limits practical applications. Previous efforts on 2D memristors have primarily focused on exploring new material systems, while damage from the metallization step remains a practical concern for the reliability of 2D memristors. Here, the impact of metallization conditions and the thickness of MoS₂films on the reliability and other device metrics of MoS₂‐based memristors is carefully studied. The statistical electrical measurements show that the reliability can be improved to 92% for yield and improved by ≈16× for average DC cycling endurance in the devices by reducing the top electrode (TE) deposition rate and increasing the thickness of MoS₂films. Intriguing convergence of switching voltages and resistance ratio is revealed by the statistical analysis of experimental switching cycles. An “effective switching layer” model compatible with both monolayer and few‐layer MoS₂, is proposed to understand the reliability improvement related to the optimization of fabrication configuration and the convergence of switching metrics. The Monte Carlo simulations help illustrate the underlying physics of endurance failure associated with cluster formation and provide additional insight into endurance improvement with device fabrication optimization. 

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2. Protons: Critical Species for Resistive Switching in Interface‐Type Memristors

   https://doi.org/10.1002/aelm.202200816  

   Kunwar, Sundar; Somodi, Chase_Bennett; Lalk, Rebecca_A; Rutherford, Bethany_X; Corey, Zachary; Roy, Pinku; Zhang, Di; Hellenbrand, Markus; Xiao, Ming; MacManus‐Driscoll, Judith_L; et al (October 2022, Advanced Electronic Materials)

   Abstract Interface‐type (IT) resistive switching (RS) memories are promising for next generation memory and computing technologies owing to the filament‐free switching, high on/off ratio, low power consumption, and low spatial variability. Although the switching mechanisms of memristors have been widely studied in filament‐type devices, they are largely unknown in IT memristors. In this work, using the simple Au/Nb:SrTiO₃(Nb:STO) as a model Schottky system, it is identified that protons from moisture are key element in determining the RS characteristics in IT memristors. The Au/Nb:STO devices show typical Schottky interface controlled current–voltage (I–V) curves with a large on/off ratio under ambient conditions. Surprisingly, in a controlled environment without protons/moisture, the largeI–Vhysteresis collapses with the disappearance of a high resistance state (HRS) and the Schottky barrier. Once the devices are re‐exposed to a humid environment, the typical largeI–Vhysteresis can be recovered within hours as the HRS and Schottky interface are restored. The RS mechanism in Au/Nb:STO is attributed to the Schottky barrier modulation by a proton assisted electron trapping and detrapping process. This work highlights the important role of protons/moisture in the RS properties of IT memristors and provides fundamental insight for switching mechanisms in metal oxides‐based memory devices. 

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3. The effect of intrinsic layer on the performance of oxide-based p-i-n heterojunctions integrating p-SnOx and n-InGaZnO

   Lee, Dong Hun; Lee, Sunghwan (May 2022, Materials Research Society)

   The discovery of oxide electronics is of increasing importance today as one of the most promising new technologies and manufacturing processes for a variety of electronic and optoelectronic applications such as next-generation displays, batteries, solar cells, and photodetectors. The high potential use seen in oxide electronics is due primarily to their high carrier mobilities and their ability to be fabricated at low temperatures. However, since the majority of oxide semiconductors are n-type oxides, current applications are limited to unipolar devices, eventually developing oxide-based bipolar devices such as p-n diodes and complementary metal-oxide semiconductors. We have contributed to wide range of oxide semiconductors and their electronics and optoelectronic device applications. Particularly, we have demonstrated n-type oxide-based thin film transistors (TFT), integrating In2O3-based n-type oxide semiconductors from binary cation materials to ternary cation species including InZnO, InGaZnO (IGZO), and InAlZnO. We have suggested channel/metallization contact strategies to achieve stable TFT performance, identified vacancy-based native defect doping mechanisms, suggested interfacial buffer layers to promote charge injection capability, and established the role of third cation species on the carrier generation and carrier transport. More recently, we have reported facile manufacturing of p-type SnOx through reactive magnetron sputtering from a Sn metal target. The fabricated p-SnOx was found to be devoid of metallic phase of Sn from x-ray photoelectron spectroscopy and demonstrated stable performance in a fully oxide based p-n heterojunction together with n-InGaZnO. The oxide-based p-n junctions exhibited a high rectification ratio greater than 103 at ±3 V, a low saturation current of ~2x10-10, and a small turn-on voltage of -0.5 V. With all the previous achievements and investigations about p-type oxide semiconductors, challenges remain for implementing p-type oxide realization. For the implementation of oxide-based p-n heterojunctions, the performance needs to be further enhanced. The current on/off ration may be limited, in our device structure, due to either high reverse saturation current (or current density) or non-ideal performance. In this study, two rational strategies are suggested to introduce an “intrinsic” layer, which is expected to reduce the reverse saturation current between p-SnOx and n-IGZO and hence increase the on/off ratio. The carrier density of n-IGZO is engineered in-situ during the sputtering process, by which compositionally homogeneous IGZO with significantly reduced carrier density is formed at the interface. Then, higher carrier density IGZO is formed continuously on the lower carrier density IGZO during the sputtering process without any exposure of the sample to the air. Alternatively, heterogeneous oxides of MgO and SiO2 are integrated into between p-SnOx and n-IGZO, by which the defects on the surface can be passivated. The interfacial properties are thoroughly investigated using transmission electron microscopy and atomic force microscopy. The I-V characteristics are compared between the set of devices integrated with two types of “intrinsic” layers. The current research results are expected to contribute to the development of p-type oxides and their industrial application manufacturing process that meets current processing requirements, such as mass production in p-type oxide semiconductors. 

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4. (Digital Presentation) Oxide Memristors Based on SiO ₂ with Cu/Ag Alloy Metallization for Neuromorphic Computing

   https://doi.org/10.1149/MA2022-0215808mtgabs  

   Qin, Fei; Song, Han Wook; Qin, Fei (October 2022, ECS Meeting Abstracts)

   By mimicking biomimetic synaptic processes, the success of artificial intelligence (AI) has been astounding with various applications such as driving automation, big data analysis, and natural-language processing.[1-4] Due to a large quantity of data transmission between the separated memory unit and the logic unit, the classical computing system with von Neumann architecture consumes excessive energy and has a significant processing delay.[5] Furthermore, the speed difference between the two units also causes extra delay, which is referred to as the memory wall.[6, 7] To keep pace with the rapid growth of AI applications, enhanced hardware systems that particularly feature an energy-efficient and high-speed hardware system need to be secured. The novel neuromorphic computing system, an in-memory architecture with low power consumption, has been suggested as an alternative to the conventional system. Memristors with analog-type resistive switching behavior are a promising candidate for implementing the neuromorphic computing system since the devices can modulate the conductance with cycles that act as synaptic weights to process input signals and store information.[8, 9] The memristor has sparked tremendous interest due to its simple two-terminal structure, including top electrode (TE), bottom electrode (BE), and an intermediate resistive switching (RS) layer. Many oxide materials, including HfO₂, Ta₂O₅, and IGZO, have extensively been studied as an RS layer of memristors. Silicon dioxide (SiO₂) features 3D structural conformity with the conventional CMOS technology and high wafer-scale homogeneity, which has benefited modern microelectronic devices as dielectric and/or passivation layers. Therefore, the use of SiO₂as a memristor RS layer for neuromorphic computing is expected to be compatible with current Si technology with minimal processing and material-related complexities. In this work, we proposed SiO₂-based memristor and investigated switching behaviors metallized with different reduction potentials by applying pure Cu and Ag, and their alloys with varied ratios. Heavily doped p-type silicon was chosen as BE in order to exclude any effects of the BE ions on the memristor performance. We previously reported that the selection of TE is crucial for achieving a high memory window and stable switching performance. According to the study which compares the roles of Cu (switching stabilizer) and Ag (large switching window performer) TEs for oxide memristors, we have selected the TE materials and their alloys to engineer the SiO₂-based memristor characteristics. The Ag TE leads to a larger memory window of the SiO₂memristor, but the device shows relatively large variation and less reliability. On the other hand, the Cu TE device presents uniform gradual switching behavior which is in line with our previous report that Cu can be served as a stabilizer, but with small on/off ratio.[9] These distinct performances with Cu and Ag metallization leads us to utilize a Cu/Ag alloy as the TE. Various compositions of Cu/Ag were examined for the optimization of the memristor TEs. With a Cu/Ag alloying TE with optimized ratio, our SiO₂based memristor demonstrates uniform switching behavior and memory window for analog switching applications. Also, it shows ideal potentiation and depression synaptic behavior under the positive/negative spikes (pulse train). In conclusion, the SiO₂memristors with different metallization were established. To tune the property of RS layer, the sputtering conditions of RS were varied. To investigate the influence of TE selections on switching performance of memristor, we integrated Cu, Ag and Cu/Ag alloy as TEs and compared the switch characteristics. Our encouraging results clearly demonstrate that SiO₂with Cu/Ag is a promising memristor device with synaptic switching behavior in neuromorphic computing applications. Acknowledgement This work was supported by the U.S. National Science Foundation (NSF) Award No. ECCS-1931088. S.L. and H.W.S. acknowledge the support from the Improvement of Measurement Standards and Technology for Mechanical Metrology (Grant No. 22011044) by KRISS. References [1] Younget al.,IEEE Computational Intelligence Magazine,vol. 13, no. 3, pp. 55-75, 2018. [2] Hadsellet al.,Journal of Field Robotics,vol. 26, no. 2, pp. 120-144, 2009. [3] Najafabadiet al.,Journal of Big Data,vol. 2, no. 1, p. 1, 2015. [4] Zhaoet al.,Applied Physics Reviews,vol. 7, no. 1, 2020. [5] Zidanet al.,Nature Electronics,vol. 1, no. 1, pp. 22-29, 2018. [6] Wulfet al.,SIGARCH Comput. Archit. News,vol. 23, no. 1, pp. 20–24, 1995. [7] Wilkes,SIGARCH Comput. Archit. News,vol. 23, no. 4, pp. 4–6, 1995. [8] Ielminiet al.,Nature Electronics,vol. 1, no. 6, pp. 333-343, 2018. [9] Changet al.,Nano Letters,vol. 10, no. 4, pp. 1297-1301, 2010. [10] Qinet al., Physica Status Solidi (RRL) - Rapid Research Letters, pssr.202200075R1, In press, 2022. 

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5. Engineered high endurance in WO ₃ -based resistive switching devices via a guided filament approach

   https://doi.org/10.1126/sciadv.adt9789  

   Yuan, Ziyi; Bakhit, Babak; Liu, Yi-Xuan; Sun, Zhuotong; I_Lampronti, Giulio; Li, Xinjuan; Fairclough, Simon M; Tsai, Benson K; Choudhury, Abhijeet; Ducati, Caterina; et al (May 2025, Science Advances)

   Resistive switching devices are promising candidates for the next generation of nonvolatile memory and neuromorphic computing applications. Despite the advantages in retention and on/off ratio, filamentary-based memristors still suffer from challenges, particularly endurance (flash being a benchmark system showing 10⁴to 10⁶ cycles) and uniformity. Here, we use WO₃as a complementary metal-oxide semiconductor–compatible switching oxide and demonstrate a proof-of-concept materials design approach to enhance endurance and device-to-device uniformity in WO₃-based memristive devices while preserving other performance metrics. These devices show stable resistive switching behavior with >10⁶ cycles, >10⁵-second retention, >10 on/off ratio, and good device-to-device uniformity, without using current compliance. All these metrics are achieved using a one-step pulsed laser deposition process to create self-assembled nanocomposite thin films that have regular guided filaments of ≈100-nanometer pitch, preformed between WO₃grains and interspersed smaller Ce₂O₃grains. 

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