State‐of‐the‐art distributed‐memory computer clusters contain multicore CPUs with 16 and more cores. The second generation of the Intel Xeon Phi many‐core processor has more than 60 cores with 16 GB of high‐performance on‐chip memory. We contrast the performance of the second‐generation Intel Xeon Phi, code‐named Knights Landing (KNL), with 68 computational cores to the latest multicore CPU Intel Skylake with 18 cores. A special‐purpose code solving a system of nonlinear reaction‐diffusion partial differential equations with several thousands of point sources modeled mathematically by Dirac delta distributions serves as realistic test bed. The system is discretized in space by the finite volume method and advanced by fully implicit time‐stepping, with a matrix‐free implementation that allows the complex model to have an extremely small memory footprint. The sample application is a seven variable model of calcium‐induced calcium release (CICR) that models the interplay between electrical excitation, calcium signaling, and mechanical contraction in a heart cell. The results demonstrate that excellent parallel scalability is possible on both hardware platforms, but that modern multicore CPUs outperform the specialized many‐core Intel Xeon Phi KNL architecture for a large class of problems such as systems of parabolic partial differential equations.
Exploring source-to-source compiler transformation of OpenMP SIMD constructs for Intel AVX and Arm SVE vector architectures
Over the past decade, SIMD (single instruction multiple data) or vector architectures have made significant advances, now existing across a wide range of devices from commodity CPUs to high performance computing (HPC) cores. Intel's AVX (Advanced Vector Extensions) architecture has been one of the most popular SIMD extensions to commodity and HPC CPUs from Intel. Over the past few years, Arm has made significant inroads with its new SVE (Scalable Vector Extension), used in the supercomputer of the top place on the Top500 list. As SIMD has become more advanced and more important, it has become equally important the compilers support these architecture extensions. In this paper, we present our approach of source-to-source compiler transformation of explicit vectorization constructs using the OpenMP SIMD directive. We present the design of a unified IR that is easily translated to AVX and SVE vector architectures. Finally, we conduct performance evaluations on Intel AVX and Arm SVE to demonstrate how this method of vectorization can bridge the gap between auto- and manual- vectorization.
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- Award ID(s):
- 2015254
- PAR ID:
- 10394960
- Date Published:
- Journal Name:
- PMAM '22: Proceedings of the Thirteenth International Workshop on Programming Models and Applications for Multicores and Manycores
- Page Range / eLocation ID:
- 11 to 20
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Conference Paper:
- https://doi.org/10.1145/3528425.3529100
