Dhar, Ashutosh, Richter, Edward, Yu, Mang, Zuo, Wei, Wang, Xiaohao, Kim, Nam Sung, and Chen, Deming. DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs. Retrieved from https://par.nsf.gov/biblio/10395077. IEEE Transactions on Computers 71.10 Web. doi:10.1109/TC.2021.3137785.

Dhar, Ashutosh, Richter, Edward, Yu, Mang, Zuo, Wei, Wang, Xiaohao, Kim, Nam Sung, & Chen, Deming. DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs. IEEE Transactions on Computers, 71 (10). Retrieved from https://par.nsf.gov/biblio/10395077. https://doi.org/10.1109/TC.2021.3137785

Dhar, Ashutosh, Richter, Edward, Yu, Mang, Zuo, Wei, Wang, Xiaohao, Kim, Nam Sung, and Chen, Deming. "DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs". IEEE Transactions on Computers 71 (10). Country unknown/Code not available. https://doi.org/10.1109/TC.2021.3137785. https://par.nsf.gov/biblio/10395077.

@article{osti_10395077,
place = {Country unknown/Code not available}, title = {DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs}, url = {https://par.nsf.gov/biblio/10395077}, DOI = {10.1109/TC.2021.3137785}, abstractNote = {}, journal = {IEEE Transactions on Computers}, volume = {71}, number = {10}, author = {Dhar, Ashutosh and Richter, Edward and Yu, Mang and Zuo, Wei and Wang, Xiaohao and Kim, Nam Sung and Chen, Deming}, }