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Interconnect materials play the critical role of routing energy and information in integrated circuits. However, established bulk conductors, such as copper, perform poorly when scaled down beyond 10 nm, limiting the scalability of logic devices. Here, a multi‐objective search is developed, combined with first‐principles calculations, to rapidly screen over 15,000 materials and discover new interconnect candidates. This approach simultaneously optimizes the bulk electronic conductivity, surface scattering time, and chemical stability using physically motivated surrogate properties accessible from materials databases. Promising local interconnects are identified that have the potential to outperform ruthenium, the current state‐of‐the‐art post‐Cu material, and also semi‐global interconnects with potentially large skin depths at the GHz operation frequency. The approach is validated on one of the identified candidates, CoPt, using both ab initio and experimental transport studies, showcasing its potential to supplant Ru and Cu for future local interconnects.
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Exploring Topological Semi-Metals for Interconnects
The size of transistors has drastically reduced over the years. Interconnects have likewise also been scaled down. Today, conventional copper (Cu)-based interconnects face a significant impediment to further scaling since their electrical conductivity decreases at smaller dimensions, which also worsens the signal delay and energy consumption. As a result, alternative scalable materials such as semi-metals and 2D materials were being investigated as potential Cu replacements. In this paper, we experimentally showed that CoPt can provide better resistivity than Cu at thin dimensions and proposed hybrid poly-Si with a CoPt coating for local routing in standard cells for compactness. We evaluated the performance gain for DRAM/eDRAM, and area vs. performance trade-off for D-Flip-Flop (DFF) using hybrid poly-Si with a thin film of CoPt. We gained up to a 3-fold reduction in delay and a 15.6% reduction in cell area with the proposed hybrid interconnect. We also studied the system-level interconnect design using NbAs, a topological semi-metal with high electron mobility at the nanoscale, and demonstrated its advantages over Cu in terms of resistivity, propagation delay, and slew rate. Our simulations revealed that NbAs could reduce the propagation delay by up to 35.88%. We further evaluated the potential system-level performance gain for NbAs-based interconnects in cache memories and observed an instructions per cycle (IPC) improvement of up to 23.8%.
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- PAR ID:
- 10416122
- Date Published:
- Journal Name:
- Journal of Low Power Electronics and Applications
- Volume:
- 13
- Issue:
- 1
- ISSN:
- 2079-9268
- Page Range / eLocation ID:
- 16
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Journal Article:
- https://doi.org/10.3390/jlpea13010016
