skip to main content

Explore Research Products in the NSF-PAR

Title: Exploring Topological Semi-Metals for Interconnects
The size of transistors has drastically reduced over the years. Interconnects have likewise also been scaled down. Today, conventional copper (Cu)-based interconnects face a significant impediment to further scaling since their electrical conductivity decreases at smaller dimensions, which also worsens the signal delay and energy consumption. As a result, alternative scalable materials such as semi-metals and 2D materials were being investigated as potential Cu replacements. In this paper, we experimentally showed that CoPt can provide better resistivity than Cu at thin dimensions and proposed hybrid poly-Si with a CoPt coating for local routing in standard cells for compactness. We evaluated the performance gain for DRAM/eDRAM, and area vs. performance trade-off for D-Flip-Flop (DFF) using hybrid poly-Si with a thin film of CoPt. We gained up to a 3-fold reduction in delay and a 15.6% reduction in cell area with the proposed hybrid interconnect. We also studied the system-level interconnect design using NbAs, a topological semi-metal with high electron mobility at the nanoscale, and demonstrated its advantages over Cu in terms of resistivity, propagation delay, and slew rate. Our simulations revealed that NbAs could reduce the propagation delay by up to 35.88%. We further evaluated the potential system-level performance gain for NbAs-based interconnects in cache memories and observed an instructions per cycle (IPC) improvement of up to 23.8%.  more » « less
Award ID(s):
2246564
NSF-PAR ID:
10416122
Author(s) / Creator(s):
; ; ; ; ; ; ;
Date Published:
Journal Name:
Journal of Low Power Electronics and Applications
Volume:
13
Issue:
1
ISSN:
2079-9268
Page Range / eLocation ID:
16
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
More Like this
  1. ; ( , 2021 United States National Committee of URSI National Radio Science Meeting (USNC-URSI NRSM))
    null (Ed.)
    The dielectric waveguide (WG) is an important building block of high-speed and high-bandwidth optical and opto-electronic interconnect networks that operate in the THz frequency regime. At the interface of Si/SiO 2 dielectric waveguides with width above w = 2.5 μm and anisotropic surface roughness, transverse electric (TE) mode surface wave propagation can experience a loss of approximately a = 2 dB/cm; however, propagation losses increase rapidly to near a = 44 dB/cm as the width decreases to w = 500 nm, due to increased interaction of surface waves and sidewall surface roughness that exhibits random distribution inherent to the manufacturing process. Previous works have developed analytic expressions for computing propagation loss in a single dielectric waveguide exhibiting random roughness. More recent works report a = 0.4 dB/cm noting the non-trivial estimation errors in previous theoretical formulations which relied on planar approximations, and highlight the discrepancy in planar approximations vs. the 3-D Volume Current Method. A challenge that remains in the path of designing nanoscale optical interconnects is the dearth of efficient 3-D stochastic computational electromagnetic (CEM) models for multiple tightly coupled optical dielectric waveguides that characterize propagation loss due to random surface roughness in waveguide sidewalls. Through a series of theoretical and numerical experiments developed in the method of finite-difference time-domain (FDTD), we aim to develop stochastic CEM models to quantify propagation loss and facilitate signal & power integrity modeling & simulation of arbitrary configurations of multiple tightly-coupled waveguides, and to gain further insights into loss mechanisms due to random surface roughness in optical interconnects. 
    more » « less
  2. ( , Micromachines)
    The development of magnetic logic devices dictates a need for a novel type of interconnect for magnetic signal transmission. Fast signal damping is one of the problems which drastically differs from conventional electric technology. Here, we describe a magnetic interconnect based on a composite multiferroic comprising piezoelectric and magnetostrictive materials. Internal signal amplification is the main reason for using multiferroic material, where a portion of energy can be transferred from electric to magnetic domains via stress-mediated coupling. The utilization of composite multiferroics consisting of piezoelectric and magnetostrictive materials offers flexibility for the separate adjustment of electric and magnetic characteristics. The structure of the proposed interconnect resembles a parallel plate capacitor filled with a piezoelectric, where one of the plates comprises a magnetoelastic material. An electric field applied across the plates of the capacitor produces stress, which, in turn, affects the magnetic properties of the magnetostrictive material. The charging of the capacitor from one edge results in the charge diffusion accompanied by the magnetization change in the magnetostrictive layer. This enables the amplitude of the magnetic signal to remain constant during the propagation. The operation of the proposed interconnects is illustrated by numerical modeling. The model is based on the Landau–Lifshitz–Gilbert equation with the electric field-dependent anisotropy term included. A variety of magnetic logic devices and architectures can benefit from the proposed interconnects, as they provide reliable and low-energy-consuming data transmission. According to the estimates, the group velocity of magnetic signals may be up to 105 m/s with energy dissipation less than 10−18 J per bit per 100 nm. The physical limits and practical challenges of the proposed approach are also discussed. 
    more » « less
  3. ; ; ( , ECS Meeting Abstracts)

    By mimicking biomimetic synaptic processes, the success of artificial intelligence (AI) has been astounding with various applications such as driving automation, big data analysis, and natural-language processing.[1-4] Due to a large quantity of data transmission between the separated memory unit and the logic unit, the classical computing system with von Neumann architecture consumes excessive energy and has a significant processing delay.[5] Furthermore, the speed difference between the two units also causes extra delay, which is referred to as the memory wall.[6, 7] To keep pace with the rapid growth of AI applications, enhanced hardware systems that particularly feature an energy-efficient and high-speed hardware system need to be secured. The novel neuromorphic computing system, an in-memory architecture with low power consumption, has been suggested as an alternative to the conventional system. Memristors with analog-type resistive switching behavior are a promising candidate for implementing the neuromorphic computing system since the devices can modulate the conductance with cycles that act as synaptic weights to process input signals and store information.[8, 9]

    The memristor has sparked tremendous interest due to its simple two-terminal structure, including top electrode (TE), bottom electrode (BE), and an intermediate resistive switching (RS) layer. Many oxide materials, including HfO2, Ta2O5, and IGZO, have extensively been studied as an RS layer of memristors. Silicon dioxide (SiO2) features 3D structural conformity with the conventional CMOS technology and high wafer-scale homogeneity, which has benefited modern microelectronic devices as dielectric and/or passivation layers. Therefore, the use of SiO2as a memristor RS layer for neuromorphic computing is expected to be compatible with current Si technology with minimal processing and material-related complexities.

    In this work, we proposed SiO2-based memristor and investigated switching behaviors metallized with different reduction potentials by applying pure Cu and Ag, and their alloys with varied ratios. Heavily doped p-type silicon was chosen as BE in order to exclude any effects of the BE ions on the memristor performance. We previously reported that the selection of TE is crucial for achieving a high memory window and stable switching performance. According to the study which compares the roles of Cu (switching stabilizer) and Ag (large switching window performer) TEs for oxide memristors, we have selected the TE materials and their alloys to engineer the SiO2-based memristor characteristics. The Ag TE leads to a larger memory window of the SiO2memristor, but the device shows relatively large variation and less reliability. On the other hand, the Cu TE device presents uniform gradual switching behavior which is in line with our previous report that Cu can be served as a stabilizer, but with small on/off ratio.[9] These distinct performances with Cu and Ag metallization leads us to utilize a Cu/Ag alloy as the TE. Various compositions of Cu/Ag were examined for the optimization of the memristor TEs. With a Cu/Ag alloying TE with optimized ratio, our SiO2based memristor demonstrates uniform switching behavior and memory window for analog switching applications. Also, it shows ideal potentiation and depression synaptic behavior under the positive/negative spikes (pulse train).

    In conclusion, the SiO2memristors with different metallization were established. To tune the property of RS layer, the sputtering conditions of RS were varied. To investigate the influence of TE selections on switching performance of memristor, we integrated Cu, Ag and Cu/Ag alloy as TEs and compared the switch characteristics. Our encouraging results clearly demonstrate that SiO2with Cu/Ag is a promising memristor device with synaptic switching behavior in neuromorphic computing applications.

    Acknowledgement

    This work was supported by the U.S. National Science Foundation (NSF) Award No. ECCS-1931088. S.L. and H.W.S. acknowledge the support from the Improvement of Measurement Standards and Technology for Mechanical Metrology (Grant No. 22011044) by KRISS.

    References

    [1] Younget al.,IEEE Computational Intelligence Magazine,vol. 13, no. 3, pp. 55-75, 2018.

    [2] Hadsellet al.,Journal of Field Robotics,vol. 26, no. 2, pp. 120-144, 2009.

    [3] Najafabadiet al.,Journal of Big Data,vol. 2, no. 1, p. 1, 2015.

    [4] Zhaoet al.,Applied Physics Reviews,vol. 7, no. 1, 2020.

    [5] Zidanet al.,Nature Electronics,vol. 1, no. 1, pp. 22-29, 2018.

    [6] Wulfet al.,SIGARCH Comput. Archit. News,vol. 23, no. 1, pp. 20–24, 1995.

    [7] Wilkes,SIGARCH Comput. Archit. News,vol. 23, no. 4, pp. 4–6, 1995.

    [8] Ielminiet al.,Nature Electronics,vol. 1, no. 6, pp. 333-343, 2018.

    [9] Changet al.,Nano Letters,vol. 10, no. 4, pp. 1297-1301, 2010.

    [10] Qinet al., Physica Status Solidi (RRL) - Rapid Research Letters, pssr.202200075R1, In press, 2022.

     
    more » « less
  4. ; ; ; ; ; ; ; ; ; ; et al ( , Advanced Materials)
    Abstract

    The interconnect half‐pitch size will reach ≈20 nm in the coming sub‐5 nm technology node. Meanwhile, the TaN/Ta (barrier/liner) bilayer stack has to be >4 nm to ensure acceptable liner and diffusion barrier properties. Since TaN/Ta occupy a significant portion of the interconnect cross‐section and they are much more resistive than Cu, the effective conductance of an ultrascaled interconnect will be compromised by the thick bilayer. Therefore, 2D layered materials have been explored as diffusion barrier alternatives. However, many of the proposed 2D barriers are prepared at too high temperatures to be compatible with the back‐end‐of‐line (BEOL) technology. In addition, as important as the diffusion barrier properties, the liner properties of 2D materials must be evaluated, which has not yet been pursued. Here, a 2D layered tantalum sulfide (TaSx) with ≈1.5 nm thickness is developed to replace the conventional TaN/Ta bilayer. The TaSxultrathin film is industry‐friendly, BEOL‐compatible, and can be directly prepared on dielectrics. The results show superior barrier/liner properties of TaSxcompared to the TaN/Ta bilayer. This single‐stack material, serving as both a liner and a barrier, will enable continued scaling of interconnects beyond 5 nm node.

     
    more » « less
  5. ; ; ; ; ; ( , IEEE Computer Architecture Letters)
    The architecture of a coarse-grained reconfigurable array (CGRA) interconnect has a significant effect on not only the flexibility of the resulting accelerator, but also its power, performance, and area. Design decisions that have complex trade-offs need to be explored to maintain efficiency and performance across a variety of evolving applications. This paper presents Canal, a Python-embedded domain-specific language (eDSL) and compiler for specifying and generating reconfigurable interconnects for CGRAs. Canal uses a graph-based intermediate representation (IR) that allows for easy hardware generation and tight integration with place and route tools. We evaluate Canal by constructing both a fully static interconnect and a hybrid interconnect with ready-valid signaling, and by conducting design space exploration of the interconnect architecture by modifying the switch box topology, the number of routing tracks, and the interconnect tile connections. Through the use of a graph-based IR for CGRA interconnects, the eDSL, and the interconnect generation system, Canal enables fast design space exploration and creation of CGRA interconnects. 
    more » « less
  • Citation Formats
  • MLA
  • APA
  • Chicago
  • BibTeX
  • Save / Share this Record
  • Send to Email