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Title: Verification of serialising instructions for security against transient execution attacks
Abstract

Transient execution attacks such as Spectre and Meltdown exploit speculative execution in modern microprocessors to leak information via cache side‐channels. Software solutions to defend against many transient execution attacks employ thelfenceserialising instruction, which does not allow instructions that come after thelfenceto execute out‐of‐order with respect to instructions that come before thelfence. However, errors and Trojans in the hardware implementation oflfencecan be exploited to compromise the software mitigations that uselfence. The aforementioned security gap has not been identified and addressed previously. The authors provide a formal method solution that addresses the verification oflfencehardware implementation. The authors also show how hardware Trojans can be designed to circumventlfenceand demonstrate that their verification approach will flag such Trojans as well. The authors have demonstrated the efficacy of our approach using RSD, which is an open source RISC‐V based superscalar out‐of‐order processor.

 
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Award ID(s):
2117190
NSF-PAR ID:
10416662
Author(s) / Creator(s):
 ;  ;  
Publisher / Repository:
DOI PREFIX: 10.1049
Date Published:
Journal Name:
IET Computers & Digital Techniques
Volume:
17
Issue:
3-4
ISSN:
1751-8601
Page Range / eLocation ID:
p. 127-140
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
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