The ever-increasing number of layers, millions of parameters,
and large data volume make deep learning workloads
resource-intensive and power-hungry. In this paper, we develop
a convolutional neural network (CNN) acceleration framework,
named MLCNN, which explores algorithm-hardware co-design
to achieve cross-layer cooperative optimization and acceleration.
MLCNN dramatically reduces computation and on-off chip
communication, improving CNN’s performance. To achieve this,
MLCNN reorders the position of nonlinear activation layers and
pooling layers, which we prove results in a negligible accuracy
loss; then the convolutional layer and pooling layer are cooptimized
by means of redundant multiplication elimination, local
addition reuse, and global addition reuse. To the best of our
knowledge, MLCNN is the first of its kind that incorporates
cooperative optimization across convolutional, activation, and
pooling layers. We further customize the MLCNN accelerator
to take full advantage of cross-layer CNN optimization to
reduce both computation and on-off chip communication. Our
analysis shows that MLCNN can significantly reduce (up to 98%)
multiplications and additions. We have implemented a prototype
of MLCNN and evaluated its performance on several widely
used CNN models using both an accelerator-level cycle and
energy model and RTL implementation. Experimental results
show that MLCNN achieves 3.2× speedup and 2.9× energy
efficiency compared with dense CNNs. MLCNN’s optimization
methods are orthogonal to other CNN acceleration techniques,
such as quantization and pruning. Combined with quantization,
our quantized MLCNN gains a 12.8× speedup and 11.3× energy
efficiency compared with DCNN.
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Towards Real-Time Segmentation on the Edge
There have been many recent attempts to extend the successes of convolutional neural networks (CNNs) from 2-dimensional (2D) image classification to 3-dimensional (3D) video recognition by exploring 3D CNNs. Considering the emerging growth of mobile or Internet of Things (IoT) market, it is essential to investigate the deployment of 3D CNNs on edge devices. Previous works have implemented standard 3D CNNs (C3D) on hardware platforms, however, they have not exploited model compression for acceleration of inference. This work proposes a hardware-aware pruning approach that can fully adapt to the loop tiling technique of FPGA design and is applied onto a novel 3D network called R(2+1)D. Leveraging the powerful ADMM, the proposed pruning method achieves simultaneous high accuracy and significant acceleration of computation on FPGA. With layer-wise pruning rates up to 10× and negligible accuracy loss, the pruned model is implemented on a Xilinx ZCU102 FPGA board, where the pruned model achieves 2.6× speedup compared with the unpruned version, and 2.3× speedup and 2.3× power efficiency improvement compared with state-of-the-art FPGA implementation of C3D.
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- NSF-PAR ID:
- 10417486
- Date Published:
- Journal Name:
- AAAI'23: The Thirty-Seventh AAAI Conference on Artificial Intelligence
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Conference Paper:
- The DOI is not currently available.
