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1. A Proxy ADC Framework for Side-Channel Secure ADC Analysis

   https://doi.org/10.1109/OJCAS.2025.3602353  

   Ash, Andrew; Hu, John (August 2025, IEEE Open Journal of Circuits and Systems)

   Shen, Y (Ed.)

   In the rapidly evolving world of hardware security, developing metrics for evaluating the security improvements of hardware designs is important. This work examines the prevailing threat model for secure analog-to-digital converter (ADC) architectures and explains how signal-to-noise ratio (SNR), root-mean-square error (RMSE), and bit-wise accuracy (BWA) are used to evaluate security improvements. The existing metrics are mathematically related through the proposed Proxy ADC framework. The proposed SNR-RMSE and BWA-RMSE relationships are validated using a power side-channel attack on a commercial ADC. The SNR-RMSE relationship achieves an average percent error of 1.69% across four trials, while the BWA-RMSE relationship achieves an average of 7.97%. Using results from past secure ADC works allows for additional demonstrations of the relationships. These relationships can estimate accuracy in a realistic attack scenario where ADC outputs cannot be measured to verify the evaluation, and recontextualize the metrics of standard ADC design for hardware security. Furthermore, the Proxy ADC framework allows for comparison of tradeoffs between designs’ security and efficiency, revealing trends to leverage for future secure architectures. 

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2. S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM

   Yang, Wu; Degada, Amit; Thapliyal, Himanshu (July 2026, 2026 IEEE Computer Society Annual Symposium on VLSI (ISVLSI))

   such as Spin-Transfer Torque (STT-MRAM) and Spin-Orbit Torque assisted (SOT-STT-MRAM) offer nonvolatility and low leakage, making them attractive for IoT systems. However, conventional MRAM read circuits face two fundamental challenges: high dynamic energy consumption and vulnerability to side-channel attacks caused by data-dependent current variations in Magnetic Tunnel Junctions (MTJs). This paper presents a Secured Adiabatic Logic Sense Amplifier (SALSA) that addresses both challenges simultaneously through circuit-device co-design. S-ALSA combines structural current balancing via a 4T-2MTJ bit cell, which eliminates read current asymmetry at the storage level, with dynamic power equalization via adiabatic charge recovery in the sensing circuit. The proposed architecture supports both STT-MRAM and SOT-STT-MRAM. Case studies using 4 × 4 MRAM macros shows up to 80% energy savings over conventional Pre-Charge Sense Amplifiers (PCSA) across IoT frequencies. Correlation Power Analysis (CPA) attacks on PRESENT-80 encryption confirm complete suppression of key leakage when S-ALSA is combined with a balanced bit cell. This work establishes a unified framework where energy efficiency and hardware security are achieved simultaneously, enabling secure and low-power IoT memory design. 

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3. A Resolution-Adaptive 8 mm ² 9.98 Gb/s 39.7 pJ/b 32-Antenna All-Digital Spatial Equalizer for mmWave Massive MU-MIMO in 65nm CMOS

   https://doi.org/10.1109/ESSCIRC53450.2021.9567843  

   Castaneda, Oscar; Boynton, Zachariah; Mirfarshbafan, Seyed Hadi; Huang, Shimin; Ye, Jamie C.; Molnar, Alyosha; Studer, Christoph (September 2021, IEEE 47th European Solid State Circuits Conference (ESSCIRC))

   All-digital millimeter-wave (mmWave) massive multi-user multiple-input multiple-output (MU-MIMO) receivers enable extreme data rates but require high power consumption. In order to reduce power consumption, this paper presents the first resolution-adaptive all-digital receiver ASIC that is able to adjust the resolution of the data-converters and baseband-processing engine to the instantaneous communication scenario. The scalable 32-antenna, 65 nm CMOS receiver occupies a total area of 8 mm 2 and integrates analog-to-digital converters (ADCs) with programmable gain and resolution, beamspace channel estimation, and a resolution-adaptive processing-in-memory spatial equalizer. With 6-bit ADC samples and a 4-bit spatial equalizer, our ASIC achieves a throughput of 9.98 Gb/s while being at least 2× more energy-efficient than state-of-the-art designs. 

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4. Massive MIMO Channel Estimation with 1-Bit Spatial Sigma-delta ADCs

   https://doi.org/10.1109/ICASSP.2019.8682842  

   Rao, Shilpa; Swindlehurst, A. Lee; Pirzadeh, Hessam (May 2019, 2019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP))

   We consider channel estimation for an uplink massive multiple input multiple output (MIMO) system where the base station (BS) uses a first-order spatial Sigma-Delta (Σ△) analog-to-digital converter (ADC) array. The Σ△ array consists of closely spaced sensors which oversample the received signal and provide a coarsely quantized (1-bit) output. We develop a linear minimum mean squared error (LMMSE) estimator based on the Bussgang decomposition that reformulates the nonlinear quantizer model using an equivalent linear model plus quantization noise. The performance of the proposed Σ△ LMMSE estimator is compared via simulation to channel estimation using standard 1-bit quantization and also infinite resolution ADCs. 

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5. EE-ACML: Energy-Efficient Adiabatic CMOS/MTJ Logic for CPA-Resistant IoT Devices

   https://doi.org/10.3390/s21227651  

   Kahleifeh, Zachary; Thapliyal, Himanshu (November 2021, Sensors)

   Internet of Things (IoT) devices have strict energy constraints as they often operate on a battery supply. The cryptographic operations within IoT devices consume substantial energy and are vulnerable to a class of hardware attacks known as side-channel attacks. To reduce the energy consumption and defend against side-channel attacks, we propose combining adiabatic logic and Magnetic Tunnel Junctions to form our novel Energy Efficient-Adiabatic CMOS/MTJ Logic (EE-ACML). EE-ACML is shown to be both low energy and secure when compared to existing CMOS/MTJ architectures. EE-ACML reduces dynamic energy consumption with adiabatic logic, while MTJs reduce the leakage power of a circuit. To show practical functionality and energy savings, we designed one round of PRESENT-80 with the proposed EE-ACML integrated with an adiabatic clock generator. The proposed EE-ACML-based PRESENT-80 showed energy savings of 67.24% at 25 MHz and 86.5% at 100 MHz when compared with a previously proposed CMOS/MTJ circuit. Furthermore, we performed a CPA attack on our proposed design, and the key was kept secret. 

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