More Like this

1. OpenExo: An open-source modular exoskeleton to augment human function

   https://doi.org/10.1126/scirobotics.adt1591  

   Williams, Jack R; Cuddeback, Chance F; Fang, Shanpu; Colley, Daniel; Enlow, Noah; Cox, Payton; Pridham, Paul; Lerner, Zachary F (June 2025, Science Robotics)

   Although the field of wearable robotic exoskeletons is rapidly expanding, there are several barriers to entry that discourage many from pursuing research in this area, ultimately hindering growth. Chief among these is the lengthy and costly development process to get an exoskeleton from conception to implementation and the necessity for a broad set of expertise. In addition, many exoskeletons are designed for a specific utility and are confined to the laboratory environment, limiting the flexibility of the designed system to adapt to answer new questions and explore new domains. To address these barriers, we present OpenExo, an open-source modular untethered exoskeleton framework that provides access to all aspects of the design process, including software, electronics, hardware, and control schemes. To demonstrate the utility of this exoskeleton framework, we performed benchtop and experimental validation testing with the system across multiple configurations, including hip-only incline assistance, ankle-only indoor and outdoor assistance, hip-and-ankle load carriage assistance, and elbow-only weightlifting assistance. All aspects of the software architecture, electrical components, hip and Bowden-cable transmission designs, and control schemes are freely available for other researchers to access, use, and modify when looking to address research questions in the field of wearable exoskeletons. Our hope is that OpenExo will accelerate the development and testing of new exoskeleton designs and control schemes while simultaneously encouraging others, including those who would have been turned away from entering the field, to explore new and unique research questions. 

   more » « less
2. Software Fault Tolerance in Real-Time Systems: Identifying the Future Research Questions

   https://doi.org/10.1145/3589950  

   Reghenzani, Federico; Guo, Zhishan; Fornaciari, William (December 2023, ACM Computing Surveys)

   Tolerating hardware faults in modern architectures is becoming a prominent problem due to the miniaturization of the hardware components, their increasing complexity, and the necessity to reduce costs. Software-Implemented Hardware Fault Tolerance approaches have been developed to improve system dependability regarding hardware faults without resorting to custom hardware solutions. However, these come at the expense of making the satisfaction of the timing constraints of the applications/activities harder from a scheduling standpoint. This article surveys the current state-of-the-art of fault tolerance approaches when used in the context of real-time systems, identifying the main challenges and the cross-links between these two topics. We propose a joint scheduling-failure analysis model that highlights the formal interactions among software fault tolerance mechanisms and timing properties. This model allows us to present and discuss many open research questions with the final aim to spur future research activities. 

   more » « less
3. A Monolithic Hardware Implementation of Kyber: Comparing Apples to Apples in PQC Candidates

   https://doi.org/10.1007/978-3-030-88238-9_6  

   Mojtaba Bisheh-Niasar, Reza Azarderakhsh and (January 2021, LatinCrypt)

   With the advent of large-scale quantum computers, factoring and discrete logarithm problems could be solved using the polynomialtime quantum algorithms. To ensure public-key security, a transition to quantum-resistant cryptographic protocols is required. Performance of hardware accelerators targeting different platforms and diverse application goals plays an important role in PQC candidates’ differentiation. Hardware accelerators based on FPGAs and ASICs also provide higher flexibility to create a very low area or ultra-high performance implementations at the high cost of the other. While the hardware/software codesign development of PQC schemes has already received an increasing research effort, a cost analysis of efficient pure hardware implementation is still lacking. On the other hand, since FPGA has various types of hardware resources, evaluating and making the accurate and fair comparison of hardware-based implementations against each other is very challenging. Without a common foundation, apples are compared to oranges. This paper demonstrates a pure hardware architecture for Kyber as one of the finalists in the third round of the NIST post-quantum cryptography standardization process. To enable real, realistic, and comparable evaluations in PQC schemes over hardware platforms, we compare our architecture over the ASIC platform as a common foundation showing that it outperforms the previous works in the literature. 

   more » « less
4. The K2 Architecture for Trustworthy Hardware Security Modules

   https://doi.org/10.1145/3625275.3625402  

   Athalye, Anish; Kaashoek, Frans; Zeldovich, Nickolai; Tassarotti, Joseph (October 2023, ACM)

   K2 is a new architecture and verification approach for hardware security modules (HSMs). The K2 architecture's rigid separation between I/O, storage, and computation over secret state enables modular proofs and allows for software development and verification independent of hardware development and verification while still providing correctness and security guarantees about the composed system. For a key step of verification, K2 introduces a new tool called Chroniton that automatically proves timing properties of software running on a particular hardware implementation, ensuring the lack of timing side channels at a cycle-accurate level. 

   more » « less
5. Volumetric DDoS Attack Detection and Mitigation using P4-DPDK

   https://doi.org/10.1109/BlackSeaCom65655.2025.11193917  

   Choueiri, Samia; Mazloum, Ali; Elizalde, Sergio; Kfoury, Elie F; Crichigno, Jorge (June 2025, IEEE)

   Distributed Denial of Service (DDoS) attacks continue to be a major threat to network environments, with their scale and complexity increasing over time. Conventional methods, such as firewalls and scrubbing centers, struggle to cope with the high traffic volumes associated with such attacks. Other recent software and hardware approaches face significant limitations in terms of scalability, flexibility, and real-time attack mitigation. This paper presents a DDoS attack detection and mitigation system that leverages the Data Plane Development Kit (DPDK) for high-speed packet processing. The system integrates a P4-based pipeline for efficient detection and mitigation directly within the data plane. The system is evaluated in a testbed environment, while varying parameters such as the attack volume, the packet size distribution, the CPU core allocations, and others. The results show that the proposed system effectively detects and mitigates DDoS attacks while maintaining high throughput and low latency, even at a high traffic rate approaching 100Gbps. Additionally, the system is compared against a widely-used open-source IDS/IPS solution. 

   more » « less