Jayasena, Aruna, Andrews, Emma, and Mishra, Prabhat. TVLA*: Test Vector Leakage Assessment on Hardware Implementations of Asymmetric Cryptography Algorithms. Retrieved from https://par.nsf.gov/biblio/10463021. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31.9 Web. doi:10.1109/TVLSI.2023.3297027.

Jayasena, Aruna, Andrews, Emma, & Mishra, Prabhat. TVLA*: Test Vector Leakage Assessment on Hardware Implementations of Asymmetric Cryptography Algorithms. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 31 (9). Retrieved from https://par.nsf.gov/biblio/10463021. https://doi.org/10.1109/TVLSI.2023.3297027

Jayasena, Aruna, Andrews, Emma, and Mishra, Prabhat. "TVLA*: Test Vector Leakage Assessment on Hardware Implementations of Asymmetric Cryptography Algorithms". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 (9). Country unknown/Code not available. https://doi.org/10.1109/TVLSI.2023.3297027. https://par.nsf.gov/biblio/10463021.

@article{osti_10463021,
place = {Country unknown/Code not available}, title = {TVLA*: Test Vector Leakage Assessment on Hardware Implementations of Asymmetric Cryptography Algorithms}, url = {https://par.nsf.gov/biblio/10463021}, DOI = {10.1109/TVLSI.2023.3297027}, abstractNote = {}, journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, volume = {31}, number = {9}, author = {Jayasena, Aruna and Andrews, Emma and Mishra, Prabhat}, }