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   Chang, Sung-En; Yuan, Geng; Lu, Alec; Sun, Mengshu; Li, Yanyu; Ma, Xiaolong; Li, Zhengang; Xie, Yanyue; Qin, Minghai; Lin, Xue; et al (January 2023, Design, Automation & Test in Europe Conference & Exhibition (DATE))
2. Scalable Low-Cost Sorting Network with Weighted Bit-Streams

   https://doi.org/10.1109/ISQED57927.2023.10129357  

   Prince, Brady; Najafi, M. Hassan; Li, Bingzhe (April 2023, 24th International Symposium on Quality Electronic Design (ISQED '23))

   Sorting is a fundamental function in many applications from data processing to database systems. For high performance, sorting-hardware based sorting designs are implemented by conventional binary or emerging stochastic computing (SC) approaches. Binary designs are fast and energy-efficient but costly to implement. SC-based designs, on the other hand, are area and power-efficient but slow and energy-hungry. So, the previous studies of the hardware-based sorting further faced scalability issues. In this work, we propose a novel scalable low-cost design for implementing sorting networks. We borrow the concept of SC for the area- and power efficiency but use weighted stochastic bit-streams to address the high latency and energy consumption issue of SC designs. A new lock and swap (LAS) unit is proposed to sort weighted bit-streams. The LAS-based sorting network can determine the result of comparing different input values early and then map the inputs to the corresponding outputs based on shorter weighted bit-streams. Experimental results show that the proposed design approach achieves much better hardware scalability than prior work. Especially, as increasing the number of inputs, the proposed scheme can reduce the energy consumption by about 3.8% - 93% compared to prior binary and SC-based designs. 

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3. SDA: Low-Bit Stable Diffusion Acceleration on Edge FPGAs

   https://doi.org/10.1109/FPL64840.2024.00044  

   Yang, Geng; Xie, Yanyue; Xue, Zhong Jia; Chang, Sung-En; Li, Yanyu; Dong, Peiyan; Lei, Jie; Xie, Weiying; Wang, Yanzhi; Lin, Xue; et al (September 2024, IEEE)
4. Low-Rank Matrix Recovery from One-Bit Comparison Information

   https://doi.org/10.1109/ICASSP.2018.8461367  

   Bose, Arindam; Ameri, Aria; Klug, Matthew; Soltanalian, Mojtaba (April 2018, 2018 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP))
5. Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM

   https://doi.org/10.1109/ISVLSI.2018.00103  

   He, Zhezhi; Angizi, Shaahin; Fan, Deliang (July 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI))

   Deep Convolution Neural Network (CNN) has achieved outstanding performance in image recognition over large scale dataset. However, pursuit of higher inference accuracy leads to CNN architecture with deeper layers and denser connections, which inevitably makes its hardware implementation demand more and more memory and computational resources. It can be interpreted as `CNN power and memory wall'. Recent research efforts have significantly reduced both model size and computational complexity by using low bit-width weights, activations and gradients, while keeping reasonably good accuracy. In this work, we present different emerging nonvolatile Magnetic Random Access Memory (MRAM) designs that could be leveraged to implement `bit-wise in-memory convolution engine', which could simultaneously store network parameters and compute low bit-width convolution. Such new computing model leverages the `in-memory computing' concept to accelerate CNN inference and reduce convolution energy consumption due to intrinsic logic-in-memory design and reduction of data communication. 

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