We report a two-step etching process involving inductively coupled plasma (ICP) etching followed by wet chemical etching to achieve smooth and vertical sidewalls, being beneficial for AlGaN-based electronic and optoelectronic devices. The influence of ICP power on the roughness of etched sidewalls is investigated. It is observed that ICP etching alone does not produce smooth sidewalls, necessitating subsequent wet chemical etching using tetramethyl ammonium hydroxide (TMAH) to enhance sidewall smoothness and reduce tilt angle. The morphological evolution of the etched sidewalls with wet etch time for the device structures is also thoroughly investigated. Consistent etch results are achieved for AlxGa1-xN alloys with Al compositions up to 70%, indicating the effectiveness of our etching process.
more »
« less
Single-Mask Fabrication of Sharp SiOx nanocones
The patterning of silicon and silicon oxide nanocones onto the surfaces of devices introduces interesting phenomena such as anti-reflection and super-transmissivity. While silicon nanocone formation is well-documented, current techniques to fabricate silicon oxide nanocones either involve complex fabrication procedures, non-deterministic placement, or poor uniformity. Here, we introduce a single-mask dry etching procedure for the fabrication of sharp silicon oxide nanocones with smooth sidewalls and deterministic distribution using electron beam lithography. Silicon oxide films deposited using plasma-enhanced chemical vapor deposition are etched using a thin alumina hard mask of selectivity > 88, enabling high aspect ratio nanocones with smooth sidewalls and arbitrary distribution across the target substrate. We further introduce a novel multi-step dry etching technique to achieve ultra-sharp amorphous silicon oxide nanocones with tip diameters of ~10 nm. The processes presented in this work may have applications in the fabrication of amorphous nanocone arrays onto arbitrary substrates or as nanoscale probes.
more »
« less
- Award ID(s):
- 2128534
- PAR ID:
- 10479626
- Publisher / Repository:
- IEEE
- Date Published:
- Journal Name:
- IEEE Transactions on Semiconductor Manufacturing
- ISSN:
- 0894-6507
- Subject(s) / Keyword(s):
- angled sidewalls, dry etch, nanocones, silica, silicon oxide, single-mask
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
More Like this
-
-
We report a method to fabricate silicon micro–nanostructures of different shapes by tuning the number of layers and the sizes of self-assembled polystyrene beads, which serve as the mask, and by tuning the reactive ion etching (RIE) time. This process is simple, scalable, and inexpensive without using any sophisticated nanomanufacturing equipment. Specifically, in this work, we demonstrate the proposed process by fabricating silicon micro- or nanoflowers, micro- or nanobells, nanopyramids, and nanotriangles using a self-assembled monolayer or bilayer of polystyrene beads as the mask. We also fabricate flexible micro–nanostructures by using silicon molds with micro–nanostructures. Finally, we demonstrate the fabrication of bandage-type electrochemical sensors with micro–nanostructured working electrodes for detecting dopamine, a neurotransmitter related to stress and neurodegenerative diseases in artificial sweat. All these demonstrations indicate that the proposed process provides a low-cost, easy-to-use approach for fabricating silicon micro–nanostructures and flexible micro–nanostructures, thus paving a way for developing wearable micro–nanostructures enabled sensors for a variety of applications in an efficient manner.more » « less
-
There is an increasing desire to utilize complex functional electronic materials such as ferroelectrics in next-generation microelectronics. As new materials are considered or introduced in this capacity, an understanding of how we can process these materials into those devices must be developed. Here, the effect of different fabrication processes on the ferroelectric and related properties of prototypical metal oxide (SrRuO3)/ferroelectric (BaTiO3)/metal oxide (SrRuO3) heterostructures is explored. Two different types of etching processes are studied, namely, wet etching of the top SrRuO3 using a NaIO4 solution and dry etching using an Ar+-ion beam (i.e., ion milling). Polarization-electric-field hysteresis loops for capacitors produced using both methods are compared. For the ion-milling process, it is found that the Ar+ beam can introduce defects into the SrRuO3/BaTiO3/SrRuO3 devices and that the milling depth strongly influences the defect level and can induce a voltage imprint on the function. Realizing that such processing approaches may be necessary, work is performed to ameliorate the imprint of the hysteresis loops via ex situ “healing” of the process-induced defects by annealing the ferroelectric material in a barium-and-oxygen-rich environment via a chemical-vapor-deposition-style process. This work provides a pathway for the nanoscale fabrication of these candidate materials for next-generation memory and logic applications.more » « less
-
Choquette, Kent D.; Lei, Chun; Graham, Luke A. (Ed.)A wafer-scale CMOS-compatible process for heterogeneous integration of III-V epitaxial material onto silicon for photonic device fabrication is presented. Transfer of AlGaAs-GaAs Vertical-Cavity Surface-Emitting Laser (VCSEL) epitaxial material onto silicon using a carrier wafer process and metallic bonding is used to form III-V islands which are subsequently processed into VCSELs. The transfer process begins with the bonding of III-V wafer pieces epitaxy-down on a carrier wafer using a temporary bonding material. Following substrate removal, precisely-located islands of material are formed using photolithography and dry etching. These islands are bonded onto a silicon host wafer using a thin-film non-gold metal bonding process and the transfer wafer is removed. Following the bonding of the epitaxial islands onto the silicon wafer, standard processing methods are used to form VCSELs with non-gold contacts. The removal of the GaAs substrate prior to bonding provides an improved thermal pathway which leads to a reduction in wavelength shift with output power under continuous-wave (CW) excitation. Unlike prior work in which fullyfabricated VCSELs are flip-chip bonded to silicon, all photonic device processing takes place after the epitaxial transfer process. The electrical and optical performance of heterogeneously integrated 850nm GaAs VCSELs on silicon is compared to their as-grown counterparts. The demonstrated method creates the potential for the integration of III-V photonic devices with silicon CMOS, including CMOS imaging arrays. Such devices could have use in applications ranging from 3D imaging to LiDAR.more » « less
-
Abstract New deposition techniques for amorphous oxide semiconductors compatible with silicon back end of line manufacturing are needed for 3D monolithic integration of thin‐film electronics. Here, three atomic layer deposition (ALD) processes are compared for the fabrication of amorphous zinc tin oxide (ZTO) channels in bottom‐gate, top‐contact n‐channel transistors. As‐deposited ZTO films, made by ALD at 150–200 °C, exhibit semiconducting, enhancement‐mode behavior with electron mobility as high as 13 cm2V−1s−1, due to a low density of oxygen‐related defects. ZTO deposited at 200 °C using a hybrid thermal‐plasma ALD process with an optimal tin composition of 21%, post‐annealed at 400 °C, shows excellent performance with a record high mobility of 22.1 cm2V–1s–1and a subthreshold slope of 0.29 V dec–1. Increasing the deposition temperature and performing post‐deposition anneals at 300–500 °C lead to an increased density of the X‐ray amorphous ZTO film, improving its electrical properties. By optimizing the ZTO active layer thickness and using a high‐kgate insulator (ALD Al2O3), the transistor switching voltage is lowered, enabling electrical compatibility with silicon integrated circuits. This work opens the possibility of monolithic integration of ALD ZTO‐based thin‐film electronics with silicon integrated circuits or onto large‐area flexible substrates.more » « less