Jiang, Zhe, Yang, Kecheng, Fisher, Nathan, Guan, Nan, Audsley, Neil C., and Dong, Zheng. Hopscotch: A Hardware-Software Co-Design for Efficient Cache Resizing on Multi-Core SoCs. Retrieved from https://par.nsf.gov/biblio/10488649. IEEE Transactions on Parallel and Distributed Systems 35.1 Web. doi:10.1109/TPDS.2023.3332711.

Jiang, Zhe, Yang, Kecheng, Fisher, Nathan, Guan, Nan, Audsley, Neil C., & Dong, Zheng. Hopscotch: A Hardware-Software Co-Design for Efficient Cache Resizing on Multi-Core SoCs. IEEE Transactions on Parallel and Distributed Systems, 35 (1). Retrieved from https://par.nsf.gov/biblio/10488649. https://doi.org/10.1109/TPDS.2023.3332711

Jiang, Zhe, Yang, Kecheng, Fisher, Nathan, Guan, Nan, Audsley, Neil C., and Dong, Zheng. "Hopscotch: A Hardware-Software Co-Design for Efficient Cache Resizing on Multi-Core SoCs". IEEE Transactions on Parallel and Distributed Systems 35 (1). Country unknown/Code not available: IEEE. https://doi.org/10.1109/TPDS.2023.3332711. https://par.nsf.gov/biblio/10488649.

@article{osti_10488649,
place = {Country unknown/Code not available}, title = {Hopscotch: A Hardware-Software Co-Design for Efficient Cache Resizing on Multi-Core SoCs}, url = {https://par.nsf.gov/biblio/10488649}, DOI = {10.1109/TPDS.2023.3332711}, abstractNote = {}, journal = {IEEE Transactions on Parallel and Distributed Systems}, volume = {35}, number = {1}, publisher = {IEEE}, author = {Jiang, Zhe and Yang, Kecheng and Fisher, Nathan and Guan, Nan and Audsley, Neil C. and Dong, Zheng}, }