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1. Pre-computing Function Results in Multi-Core and Many-Core Processors

   https://doi.org/10.1109/ICPPW.2011.46  

   Herrmann, Edward C.; Janga, Prudhvi; Wilsey, Philip A. (September 2011, International Workshop on Parallel Software Tools and Tool Infrastructures (PSTI 2011))

   In recent years, the number of hardware supported threads in desktop processors has increased dramatically. All but the very lowest cost netbooks and embedded processors now have at least dual cores and soon systems supporting upwards of 8 to 16 hardware threads are likely to be commonplace. Unfortunately, it will be difficult to take full advantage of the parallelism emerging processors will be able to provide. To help address this issue, we are investigating mechanisms to pre-compute function results in separate threads running concurrently with the main program thread. The concurrent threads are forked automatically and without program modification. A critical component for the success of this idea is an ability to build a background thread that can pre-compute usable results in some effective manner. For some support functions (dynamic memory) exact arguments predictions for the function pre-computation are not necessary, for others (trigonometric functions) they are. In work with dynamic memory, we are able to pre-compute memory blocks and show modest speedup: saving approximately 25% of the dynamic memory costs. In studies with predicting argument values to trigonometric functions, we show that learning algorithms are able to successfully predict the next argument values approximately 44% of the time. 

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2. On Carbon Replacing the Core in Classical Semiconductor Core/ZnS Quantum Dots

   https://doi.org/10.21127/yaoyigc20240001  

   Liang, W; Sheriff, K; Singh, B; Qian, H; Dumra, S; Collins, J; Yerra, S; Yang, L; Sun, Y-P (January 2024, General Chemistry)
3. Dynamically Adjusting Core Frequencies to Accelerate Time Warp Simulations in Many-Core Processors

   https://doi.org/10.1109/PADS.2012.15  

   Child, Ryan; Wilsey, Philip (July 2012, Workshop on Principles of Advanced and Distributed Simulation)

   Time Warp synchronized parallel discrete event simulators are organized to operate asynchronously and aggressively without explicit synchronization between the concurrently executing simulators. In place of an explicit synchronization mechanism, the concurrent simulators maintain a common virtual clock model and implement a rollback/recovery mechanism to restore causal order when out-of order events are detected. When the critical path of execution of the simulation is balanced across these parallel simulators, this can result in a highly effective, lightweight synchronization mechanism. However, imbalances in the workload across the parallel simulators can result in excessive rollback at some nodes and ultimately result in an overall slowing of the simulation as prematurely computed and transmitted events are processed. On small shared memory multi-core systems, a lowest timestamp first scheduling policy can effectively balance the workload. However, on larger many-core chips, conventional load balancing and workload migration will once again become necessary. Fortunately, emerging many-core chips contain some interesting features that can potentially be exploited to improve the performance of parallel simulations. For example, the Intel Single-chip Cloud Computer (SCC) provides mechanisms that a running application can use to adjust the frequency/voltage of different regions (called islands) of the chip. These islands are network and processing core centric and thus, in a Time Warp simulation, one can increase the frequency of the cores executing threads on the critical path (those experiencing infrequent rollback) and decrease the frequency of the cores executing threads off the critical path (those experiencing excessive rollback). This paper investigates the run-time control and adjustment of core frequency in an AMD Phenom II X6 multi-core processor to explore and demonstrate that the dynamic run-time control of core frequency can sometimes improve the performance of a Time Warp synchronized parallel simulation. 

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4. Defects in bent-core liquid crystals

   https://doi.org/10.1080/21680396.2022.2086932  

   Jákli, Antal; Nastishin, Yuriy; Lavrentovich, Oleg D. (July 2022, Liquid Crystals Reviews)

   Topological defects and defect phases of rigid and flexibly bent-shaped liquid crystals are reviewed with emphasis on how they are affected by the departure of molecular shapes from a simple rod. The review discusses defects in bent-core uniaxial and hypothetical biaxial nematics, twist-bend nematic, and various frustrated layered bent-core liquid crystals, such as twist-grain boundary phase, nanoscale helical nanofilament phase, and the so-called B7 textures with helical ribbons. 

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5. Equatorially trapped waves in Earth’s core

   https://doi.org/10.1093/gji/ggz233  

   Buffett, Bruce; Matsui, Hiroaki (May 2019, Geophysical Journal International)