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Title: Thermal-Aware SoC Macro Placement and Multi-chip Module Design Optimization with Bayesian Optimization
Award ID(s):
2137288 2137283 2137259 2345055
PAR ID:
10496488
Author(s) / Creator(s):
; ; ; ; ; ;
Publisher / Repository:
IEEE
Date Published:
ISBN:
979-8-3503-3498-2
Page Range / eLocation ID:
935 to 942
Format(s):
Medium: X
Location:
Orlando, FL, USA
Sponsoring Org:
National Science Foundation
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