Li, Xiaoling, Chen, Hao, Paul, Riya, Mukherjee, Shilpi, Du, Xia, Cuzner, Robert, Song, Xiaoqing, Zhao, Yue, and Mantooth, H. Alan. A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction. Retrieved from https://par.nsf.gov/biblio/10499071. Web. doi:10.1109/APEC43580.2023.10131485.

Li, Xiaoling, Chen, Hao, Paul, Riya, Mukherjee, Shilpi, Du, Xia, Cuzner, Robert, Song, Xiaoqing, Zhao, Yue, & Mantooth, H. Alan. A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction. Retrieved from https://par.nsf.gov/biblio/10499071. https://doi.org/10.1109/APEC43580.2023.10131485

Li, Xiaoling, Chen, Hao, Paul, Riya, Mukherjee, Shilpi, Du, Xia, Cuzner, Robert, Song, Xiaoqing, Zhao, Yue, and Mantooth, H. Alan. "A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction". Country unknown/Code not available: IEEE. https://doi.org/10.1109/APEC43580.2023.10131485. https://par.nsf.gov/biblio/10499071.

@article{osti_10499071,
place = {Country unknown/Code not available}, title = {A 10 kV SiC Power Module Stacked Substrate Design with Patterned Middle-layer for Partial Discharge Reduction}, url = {https://par.nsf.gov/biblio/10499071}, DOI = {10.1109/APEC43580.2023.10131485}, abstractNote = {}, journal = {}, publisher = {IEEE}, author = {Li, Xiaoling and Chen, Hao and Paul, Riya and Mukherjee, Shilpi and Du, Xia and Cuzner, Robert and Song, Xiaoqing and Zhao, Yue and Mantooth, H. Alan}, }