Venkataramanaiah, Shreyas Kolala, Meng, Jian, Suh, Han-Sok, Yeo, Injune, Saikia, Jyotishman, Cherupally, Sai Kiran, Zhang, Yichi, Zhang, Zhiru, and Seo, Jae-Sun. A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity. Retrieved from https://par.nsf.gov/biblio/10511028. IEEE Journal of Solid-State Circuits 58.7 Web. doi:10.1109/JSSC.2023.3269148.

Venkataramanaiah, Shreyas Kolala, Meng, Jian, Suh, Han-Sok, Yeo, Injune, Saikia, Jyotishman, Cherupally, Sai Kiran, Zhang, Yichi, Zhang, Zhiru, & Seo, Jae-Sun. A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity. IEEE Journal of Solid-State Circuits, 58 (7). Retrieved from https://par.nsf.gov/biblio/10511028. https://doi.org/10.1109/JSSC.2023.3269148

Venkataramanaiah, Shreyas Kolala, Meng, Jian, Suh, Han-Sok, Yeo, Injune, Saikia, Jyotishman, Cherupally, Sai Kiran, Zhang, Yichi, Zhang, Zhiru, and Seo, Jae-Sun. "A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity". IEEE Journal of Solid-State Circuits 58 (7). Country unknown/Code not available: IEEE. https://doi.org/10.1109/JSSC.2023.3269148. https://par.nsf.gov/biblio/10511028.

@article{osti_10511028,
place = {Country unknown/Code not available}, title = {A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity}, url = {https://par.nsf.gov/biblio/10511028}, DOI = {10.1109/JSSC.2023.3269148}, abstractNote = {}, journal = {IEEE Journal of Solid-State Circuits}, volume = {58}, number = {7}, publisher = {IEEE}, author = {Venkataramanaiah, Shreyas Kolala and Meng, Jian and Suh, Han-Sok and Yeo, Injune and Saikia, Jyotishman and Cherupally, Sai Kiran and Zhang, Yichi and Zhang, Zhiru and Seo, Jae-Sun}, }