Maximizing profits while minimizing risk in a technologically advanced silicon industry has motivated the globalization of the fabrication process and electronic hardware supply chain. However, with the increasing magnitude of successful hardware attacks, the security of many hardware IPs has been compromised. Many existing security works have focused on resolving a single vulnerability while neglecting other threats. This motivated to propose a novel approach for securing hardware IPs during the fabrication process and supply chain via logic obfuscation by utilizing emerging spin-based devices. Our proposed dynamic obfuscation approach uses reconfigurable logic and interconnects blocks (RIL-Blocks), consisting of Magnetic Random Access Memory (MRAM)-based Look Up Tables and switch boxes flexibility and resiliency against state-of-the-art SAT-based attacks and power side-channel attacks while incurring a small overhead. The proposed Scan Enabled Obfuscation circuitry obfuscates the oracle circuit’s responses and further fortifies the logic and routing obfuscation provided by the RIL-Blocks, resembling a defense-in-depth approach. The empirical evaluation of security provided by the proposed RIL-Blocks on the ISCAS benchmark and common evaluation platform (CEP) circuit shows that resiliency comes with reduced overhead while providing resiliency to various hardware security threats.
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This content will become publicly available on April 1, 2025
Optimized and Automated Secure IC Design Flow: A Defense-in-Depth Approach
The globalization of the manufacturing process and
the supply chain for electronic hardware has been driven by
the need to maximize profitability while lowering risk in a
technologically advanced silicon sector. However, many hardware
IPs’ security features have been broken because of the rise in
successful hardware attacks. Existing security efforts frequently
ignore numerous dangers in favor of fixing a particular vulnerability. This inspired the development of a unique method
that uses emerging spin-based devices to obfuscate circuitry to
secure hardware intellectual property (IP) during fabrication and
the supply chain. We propose an Optimized and Automated
Secure IC (OASIC) Design Flow, a defense-in-depth approach
that can minimize overhead while maximizing security. Our
EDA tool flow uses a dynamic obfuscation method that employs
dynamic lockboxes, which include switch boxes and magnetic
random access memory (MRAM)-based look-up tables (LUT)
while offering minimal overhead and being flexible and resilient
against modern SAT-based attacks and power side-channel
attacks. An EDA tool flow for optimized lockbox insertion is
also developed to generate SAT-resilient design netlists with the
least power and area overhead. PPA metrics and security (SAT
attack time) are provided to the designer for each lockbox
insertion run. A verification methodology is provided to verify
locked and unlocked designs for functional correctness. Finally,
we use ISCAS’85 benchmarks to show that the EDA tool flow
provides a secure hardware netlist with maximum security while
considering power and area constraints. Our results indicate that
the proposed OASIC design flow can maximize security while
incurring less than 15% area overhead and maintaining a similar
power footprint compared to the original design. OASIC design
flow demonstrates improved performance as design size increases,
which demonstrates the scalability of the proposed approach.
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- Award ID(s):
- 2213430
- PAR ID:
- 10517905
- Publisher / Repository:
- IEEE
- Date Published:
- Journal Name:
- IEEE Transactions on Circuits and Systems I: Regular Papers
- ISSN:
- 1549-8328
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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