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Stochastic computing (SC) is a digital design paradigm that foregoes the conventional binary encoding in favor of pseudo-random bitstreams. Stochastic circuits operate on the probability values of bitstreams, and often achieve low power, low area, and fault-tolerant computation. Most SC designs rely on the input bitstreams being independent or uncorrelated to obtain the best results. However, circuits have also been proposed that exploit deliberately correlated bitstreams to improve area or accuracy. In such cases, different sub-circuits may have different correlation requirements. A major barrier to multi-layer or hierarchical stochastic circuit design has been understanding how correlation propagates while meeting the correlation requirements for all its sub-circuits. In this paper, we introduce correlation matrices and extensions to probability transfer matrix (PTM) algebra to analyze complex correlation behavior, thereby alleviating the need for computationally intensive bit-wise simulation. We apply our new correlation analysis to two multi-layer SC image processing and neural network circuits and show that it helps designers to systematically reduce correlation error.
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Mitigating the Correlation Problem in Multi-Layer Stochastic Circuits
Abstract—Stochastic computing is a low-cost non-standard computer architecture that processes pseudo-random bitstreams. Its effectiveness, and that of other probabilistic methods, requires maintaining desired levels of correlation among interacting input bitstreams, for example, SCC = 0 or SCC = +1, where SCC is the stochastic cross-correlation metric. Correlation errors are systematic (bias-causing) errors that cannot be corrected by increasing bitstream length. A typical stochastic design C1 only controls correlation at its primary input lines. This is a fairly straightforward task, however it limits the scope of SC to “single layer,” usually combinational, designs. In situations where a second processing layer C2 follows C1, the output correlation of C1 must satisfy the input correlation needs of C2. This can be done by inserting a (sequential) correlation control layer S12 between C1 and C2, which incurs high area and delay overhead. S12 transforms intralayer bitstreams Z with unknown or undesired SCC values into numerically equivalent ones Z* with desired correlation. The fundamental problem of designing C1 to produce Z* directly, thereby dispensing with S12, which apparently has not been considered before, is addressed in this paper. We focus on two- layer designs C1C2 requiring SCC = +1 between layers, and present a method called COMAX for (re)designing C1 so that it outputs bitstreams with correlation that is as close as possible to +1. We demonstrate on a representative image processing application that, compared to alternative correlation control techniques, COMAX reduces area by about 50% without reducing output image quality.
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- Award ID(s):
- 2006704
- PAR ID:
- 10518944
- Publisher / Repository:
- IEEE
- Date Published:
- ISBN:
- 979-8-3503-8204-4
- Page Range / eLocation ID:
- 1 to 10
- Format(s):
- Medium: X
- Location:
- San Diego, CA, USA
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
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Accepted Manuscript1.0
- Conference Paper:
- https://doi.org/10.1109/ICRC60800.2023.10386939
