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Title: Invited Paper: Verilog-to-PyG - A Framework for Graph Learning and Augmentation on RTL Designs
Award ID(s):
2349670 2350186 2349461
PAR ID:
10520484
Author(s) / Creator(s):
; ; ;
Publisher / Repository:
2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)
Date Published:
ISBN:
979-8-3503-2225-5
Page Range / eLocation ID:
1 to 4
Format(s):
Medium: X
Location:
San Francisco, CA, USA
Sponsoring Org:
National Science Foundation
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