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   https://doi.org/10.1109/DAC63849.2025.11133406  

   Nadimi, Bardia; Boutaib, Ghali Omar; Zheng, Hao (June 2025, IEEE)

   This paper proposes a novel method for automatically inferring message flow specifications from the communication traces of a system-on-chip (SoC) design that captures messages exchanged among the components during a system execution. The inferred message flows characterize the communication and coordination of components in a system design for realizing various system functions, and they are essential for SoC validation and debugging. The proposed method relieves the burden of manual development and maintenance of such specifications on human designers. Our method also uses a new accuracy metric, acceptance ratio, to evaluate the quality of the mined specifications instead of the specification size often used in the previous work, enabling more accurate specifications to be mined. Furthermore, this paper introduces the concept of essential causalities to enhance the accuracy of the message flow mining and accelerate the mining process. The effectiveness of the proposed method is evaluated on both synthetic traces and traces generated from executing several system models in GEM5. In both cases, the proposed method achieves superior accuracies compared to a previous approach. Additionally, this paper includes some practical use cases. 

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2. Analysis and Verilog-A Modeling of Floating-Gate Transistors

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   Nowshin_Chowdhury, Sayma; Chen, Matthew; Shah, Sahil (January 2025, IEEE Open Journal of Circuits and Systems)
3. Benchmarking Large Language Models for Automated Verilog RTL Code Generation

   https://doi.org/10.23919/DATE56975.2023.10137086  

   Thakur, Shailja; Ahmad, Baleegh; Fan, Zhenxing; Pearce, Hammond; Tan, Benjamin; Karri, Ramesh; Dolan-Gavitt, Brendan; Garg, Siddharth (April 2023, 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE))

   Automating hardware design could obviate a signif-icant amount of human error from the engineering process and lead to fewer errors. Verilog is a popular hardware description language to model and design digital systems, thus generating Verilog code is a critical first step. Emerging large language models (LLMs) are able to write high-quality code in other programming languages. In this paper, we characterize the ability of LLMs to generate useful Verilog. For this, we fine-tune pre-trained LLMs on Verilog datasets collected from GitHub and Verilog textbooks. We construct an evaluation framework comprising test-benches for functional analysis and a flow to test the syntax of Verilog code generated in response to problems of varying difficulty. Our findings show that across our problem scenarios, the fine-tuning results in LLMs more capable of producing syntactically correct code (25.9% overall). Further, when analyzing functional correctness, a fine-tuned open-source CodeGen LLM can outperform the state-of-the-art commercial Codex LLM (6.5% overall). We release our training/evaluation scripts and LLM checkpoints as open source contributions. 

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4. Well-Posed Verilog-A Compact Model for Phase Change Memory

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   Kulkarni, Shruti R.; Kadetotad, Deepak Vinayak; Seo, Jae-sun; Rajendran, Bipin (September 2018, 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD))
5. MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs

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   Abdelatty, Manar; Ma, Jingxiao; Reda, Sherief (January 2025, ACM)