Li, Ziru, Zheng, Qilin, Ku, Jonathan, Taylor, Brady, and Li, Hai. TFSRAM: A 249.8TOPS/W Timing-to-First-Spike Compute-in-Memory Neuromorphic Processing Engine With Twin-Column SRAM Synapses. Retrieved from https://par.nsf.gov/biblio/10590973. IEEE Transactions on Circuits and Systems for Artificial Intelligence 1.1 Web. doi:10.1109/TCASAI.2024.3452649.

Li, Ziru, Zheng, Qilin, Ku, Jonathan, Taylor, Brady, & Li, Hai. TFSRAM: A 249.8TOPS/W Timing-to-First-Spike Compute-in-Memory Neuromorphic Processing Engine With Twin-Column SRAM Synapses. IEEE Transactions on Circuits and Systems for Artificial Intelligence, 1 (1). Retrieved from https://par.nsf.gov/biblio/10590973. https://doi.org/10.1109/TCASAI.2024.3452649

Li, Ziru, Zheng, Qilin, Ku, Jonathan, Taylor, Brady, and Li, Hai. "TFSRAM: A 249.8TOPS/W Timing-to-First-Spike Compute-in-Memory Neuromorphic Processing Engine With Twin-Column SRAM Synapses". IEEE Transactions on Circuits and Systems for Artificial Intelligence 1 (1). Country unknown/Code not available: IEEE. https://doi.org/10.1109/TCASAI.2024.3452649. https://par.nsf.gov/biblio/10590973.

@article{osti_10590973,
place = {Country unknown/Code not available}, title = {TFSRAM: A 249.8TOPS/W Timing-to-First-Spike Compute-in-Memory Neuromorphic Processing Engine With Twin-Column SRAM Synapses}, url = {https://par.nsf.gov/biblio/10590973}, DOI = {10.1109/TCASAI.2024.3452649}, abstractNote = {}, journal = {IEEE Transactions on Circuits and Systems for Artificial Intelligence}, volume = {1}, number = {1}, publisher = {IEEE}, author = {Li, Ziru and Zheng, Qilin and Ku, Jonathan and Taylor, Brady and Li, Hai}, }