Pei, Zhenlin, Liu, Hsiao-Hsuan, Mayahinia, Mahta, Tahoori, Mehdi B, Catthoor, Francky, Tőkei, Zsolt, Abdi, Dawit Burusie, Myers, James, and Pan, Chenyun. Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus. Retrieved from https://par.nsf.gov/biblio/10599095. IEEE Transactions on Circuits and Systems I: Regular Papers 71.10 Web. doi:10.1109/TCSI.2024.3438164.

Pei, Zhenlin, Liu, Hsiao-Hsuan, Mayahinia, Mahta, Tahoori, Mehdi B, Catthoor, Francky, Tőkei, Zsolt, Abdi, Dawit Burusie, Myers, James, & Pan, Chenyun. Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus. IEEE Transactions on Circuits and Systems I: Regular Papers, 71 (10). Retrieved from https://par.nsf.gov/biblio/10599095. https://doi.org/10.1109/TCSI.2024.3438164

Pei, Zhenlin, Liu, Hsiao-Hsuan, Mayahinia, Mahta, Tahoori, Mehdi B, Catthoor, Francky, Tőkei, Zsolt, Abdi, Dawit Burusie, Myers, James, and Pan, Chenyun. "Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus". IEEE Transactions on Circuits and Systems I: Regular Papers 71 (10). Country unknown/Code not available: IEEE. https://doi.org/10.1109/TCSI.2024.3438164. https://par.nsf.gov/biblio/10599095.

@article{osti_10599095,
place = {Country unknown/Code not available}, title = {Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus}, url = {https://par.nsf.gov/biblio/10599095}, DOI = {10.1109/TCSI.2024.3438164}, abstractNote = {}, journal = {IEEE Transactions on Circuits and Systems I: Regular Papers}, volume = {71}, number = {10}, publisher = {IEEE}, author = {Pei, Zhenlin and Liu, Hsiao-Hsuan and Mayahinia, Mahta and Tahoori, Mehdi B and Catthoor, Francky and Tőkei, Zsolt and Abdi, Dawit Burusie and Myers, James and Pan, Chenyun}, }