Negi, Shubham, Saxena, Utkarsh, Sharma, Deepika, Victor, Jeffry, Ahmed, Imtiaz, Gupta, Sumeet Kumar, and Roy, Kaushik. Algorithm Hardware Co-Design for ADC-Less Compute In-Memory Accelerator. Retrieved from https://par.nsf.gov/biblio/10611612. IEEE Transactions on Circuits and Systems for Artificial Intelligence 1.2 Web. doi:10.1109/TCASAI.2024.3495587.

Negi, Shubham, Saxena, Utkarsh, Sharma, Deepika, Victor, Jeffry, Ahmed, Imtiaz, Gupta, Sumeet Kumar, & Roy, Kaushik. Algorithm Hardware Co-Design for ADC-Less Compute In-Memory Accelerator. IEEE Transactions on Circuits and Systems for Artificial Intelligence, 1 (2). Retrieved from https://par.nsf.gov/biblio/10611612. https://doi.org/10.1109/TCASAI.2024.3495587

Negi, Shubham, Saxena, Utkarsh, Sharma, Deepika, Victor, Jeffry, Ahmed, Imtiaz, Gupta, Sumeet Kumar, and Roy, Kaushik. "Algorithm Hardware Co-Design for ADC-Less Compute In-Memory Accelerator". IEEE Transactions on Circuits and Systems for Artificial Intelligence 1 (2). Country unknown/Code not available: IEEE. https://doi.org/10.1109/TCASAI.2024.3495587. https://par.nsf.gov/biblio/10611612.

@article{osti_10611612,
place = {Country unknown/Code not available}, title = {Algorithm Hardware Co-Design for ADC-Less Compute In-Memory Accelerator}, url = {https://par.nsf.gov/biblio/10611612}, DOI = {10.1109/TCASAI.2024.3495587}, abstractNote = {}, journal = {IEEE Transactions on Circuits and Systems for Artificial Intelligence}, volume = {1}, number = {2}, publisher = {IEEE}, author = {Negi, Shubham and Saxena, Utkarsh and Sharma, Deepika and Victor, Jeffry and Ahmed, Imtiaz and Gupta, Sumeet Kumar and Roy, Kaushik}, }