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1. Comparative evaluation of analogue front-end designs for the CMS Inner Tracker at the High Luminosity LHC

   https://doi.org/10.1088/1748-0221/16/12/P12014  

   Adam, W.; Bergauer, T.; Blöch, D.; Dragicevic, M.; Frühwirth, R.; Hinger, V.; Steininger, H.; Beaumont, W.; Di Croce, D.; Janssen, X.; et al (December 2021, Journal of Instrumentation)

   Abstract The CMS Inner Tracker, made of silicon pixel modules, will be entirely replaced prior to the start of the High Luminosity LHC period. One of the crucial components of the new Inner Tracker system is the readout chip, being developed by the RD53 Collaboration, and in particular its analogue front-end, which receives the signal from the sensor and digitizes it. Three different analogue front-ends (Synchronous, Linear, and Differential) were designed and implemented in the RD53A demonstrator chip. A dedicated evaluation program was carried out to select the most suitable design to build a radiation tolerant pixel detector able to sustain high particle rates with high efficiency and a small fraction of spurious pixel hits. The test results showed that all three analogue front-ends presented strong points, but also limitations. The Differential front-end demonstrated very low noise, but the threshold tuning became problematic after irradiation. Moreover, a saturation in the preamplifier feedback loop affected the return of the signal to baseline and thus increased the dead time. The Synchronous front-end showed very good timing performance, but also higher noise. For the Linear front-end all of the parameters were within specification, although this design had the largest time walk. This limitation was addressed and mitigated in an improved design. The analysis of the advantages and disadvantages of the three front-ends in the context of the CMS Inner Tracker operation requirements led to the selection of the improved design Linear front-end for integration in the final CMS readout chip. 

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2. Stakeholder Engagement With Prototypes During Front-End Medical Device Design: Who Is Engaged With What Prototype?

   https://doi.org/10.1115/DMD2020-9020  

   Coulentianos, Marianna J.; Rodriguez-Calero, Ilka; Daly, Shanna R.; Sienko, Kathleen H. (January 2020, 2020 Design of Medical Devices Conference)

   null (Ed.)

   Abstract Stakeholder engagement with prototypes during the front-end phases of medical device design can support problem identification, problem definition, and early concept generation. This study examined what prototypes were leveraged to engage specific types of stakeholders during front-end medical device design. Analysis of semi-structured interviews with 22 design practitioners in the medical device industry revealed some common associations of prototype choice for particular stakeholders. A few associations are highlighted: designers engaged users with physical three-dimensional (3D) prototypes, financial decision-makers with physical 3D and two-dimensional (2D) prototypes, government and regulatory stakeholders with 2D prototypes, and expert advisors with digital 3D prototypes. The rationale provided by practitioners revealed the intentional selection of prototype form for specific stakeholder engagements. 

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3. A Nonuniform Sampling Lifetime Estimation Technique for Luminescent Oxygen Measurements

   https://doi.org/10.1109/ESSCIRC55480.2022.9911496  

   Costanzo, Ian; Sen, Devdip; McNeill, John; Guler, Ulkuhan (September 2022, IEEE 48th European Solid State Circuits Conference (ESSCIRC))

   This paper presents a nonuniform sampling technique for measuring the lifetime of luminescent materials for oxygen sensing. The system features a switched-capacitor circuit to implement fixed-voltage steps for quantization, enabling long integration times without saturating the front-end amplifier. A control circuit automatically tunes the light emitting diode (LED) excitation pulses to avoid overpowering or starving the front end as photodiode current varies with changes in the partial pressure of oxygen. Time gating of the front-end integrator removes the need for optical filtering. The analog front end (AFE) has a gain bandwidth product of 10 MHz and an input-referred noise of 124 μVrms (measured 200 Hz - 100 kHz). The circuit was realized in 180 nm CMOS technology. The AFE and LED driver consume a maximum of 16 μJ per calculation. We have demonstrated the entire system's functionality by measuring oxygen concentrations from 0 to 240 mmHg in a controlled gas vessel. The results indicate satisfactory linearity on a Stern-Volmer plot covering the human-relevant range of 50 to 150 mmHg. 

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4. PDIP: Priority Directed Instruction Prefetching

   https://doi.org/10.1145/3620665.3640394  

   Godala, Bhargav Reddy; Ramesh, Sankara Prasad; Pokam, Gilles A; Stark, Jared; Seznec, Andre; Tullsen, Dean; August, David I (April 2024, ACM)

   Modern server workloads have large code footprints which are prone to front-end bottlenecks due to instruction cache capacity misses. Even with the aggressive fetch directed instruction prefetching (FDIP), implemented in modern processors, there are still significant front-end stalls due to I-Cache misses. A major portion of misses that occur on a BPU-predicted path are tolerated by FDIP without causing stalls. Prior work on instruction prefetching, however, has not been designed to work with FDIP processors. Their singular goal is reducing I-Cache misses, whereas FDIP processors are designed to tolerate them. Designing an instruction prefetcher that works in conjunction with FDIP requires identifying the fraction of cache misses that impact front-end performance (that are not fully hidden by FDIP), and only targeting them. In this paper, we propose Priority Directed Instruction Prefetching (PDIP), a novel instruction prefetching technique that complements FDIP by issuing prefetches for only targets where FDIP struggles - along the resteer path of front-end stall-causing events. PDIP identifies these targets and associates them with a trigger for future prefetch. At a 43.5KB budget, PDIP achieves up to 5.1% IPC speedup on important workloads such as cassandra and a geomean IPC speedup of 3.2% across 16 benchmarks. 

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5. Cache on Track (CoT): Decentralized Elastic Caches for Cloud Environments

   Zakhary, V.; Lim, L.; Agrawal, D.; El Abbadi, A. (March 2021, International Conference on Extending Database Technology)

   Velegrakis, Y.; Zeinalipour-Yazti, D.; Chrysanthis, P.K.; Guerra, F. (Ed.)

   Distributed caches are widely deployed to serve social networks and web applications at billion-user scales. This paper presents Cache-on-Track (CoT), a decentralized, elastic, and predictive caching framework for cloud environments. CoT proposes a new cache replacement policy specifically tailored for small front-end caches that serve skewed workloads with small update percentage. Small front-end caches are mainly used to mitigate the load-imbalance across servers in the distributed caching layer. Front-end servers use a heavy hitter tracking algorithm to continuously track the top-k hot keys. CoT dynamically caches the top-C hot keys out of the tracked keys. CoT’s main advantage over other replacement policies is its ability to dynamically adapt its tracker and cache sizes in response to workload distribution changes. Our experiments show that CoT’s replacement policy consistently outperforms the hit-rates of LRU, LFU, and ARC for the same cache size on different skewed workloads. Also, CoT slightly outperforms the hit-rate of LRU-2 when both policies are configured with the same tracking (history) size. CoT achieves server size load-balance with 50% to 93.75% less front-end cache in comparison to other replacement policies. Finally, experiments show that CoT’s resizing algorithm successfully auto-configures the tracker and cache sizes to achieve back-end load-balance in the presence of workload distribution changes. 

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