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1. Mitigating Voltage Drop in Resistive Memories by Dynamic RESET Voltage Regulation and Partition RESET

   https://doi.org/10.1109/HPCA47549.2020.00031  

   Zokaee, Farzaneh; Jiang, Lei (February 2020, IEEE International Symposium on High Performance Computer Architecture)

   The emerging resistive random access memory (ReRAM) technology has been deemed as one of the most promising alternatives to DRAM in main memories, due to its better scalability, zero cell leakage and short read latency. The cross-point (CP) array enables ReRAM to obtain the theoretical minimum 4F^2 cell size by placing a cell at the cross-point of a word-line and a bit-line. However, ReRAM CP arrays suffer from large sneak current resulting in significant voltage drop that greatly prolongs the array RESET latency. Although prior works reduce the voltage drop in CP arrays, they either substantially increase the array peripheral overhead or cannot work well with wear leveling schemes. In this paper, we propose two array micro-architecture level techniques, dynamic RESET voltage regulation (DRVR) and partition RESET (PR), to mitigate voltage drop on both bit-lines and word-lines in ReRAM CP arrays. DRVR dynamically provides higher RESET voltage to the cells far from the write driver and thus encountering larger voltage drop on a bit-line, so that all cells on a bit-line share approximately the same latency during RESETs. PR decides how many and which cells to reset online to partition the CP array into multiple equivalent circuits with smaller word-line resistance and voltage drop. Because DRVR and PR greatly reduce the array RESET latency, the ReRAM-based main memory lifetime under the worst case non-stop write traffic significantly decreases. To increase the CP array endurance, we further upgrade DRVR by providing lower RESET voltage to the cells suffering from less voltage drop on a word-line. Our experimental results show that, compared to the combination of prior voltage drop reduction techniques, our DRVR and PR improve the system performance by 11.7% and decrease the energy consumption by 46% averagely, while still maintaining >10-year main memory system lifetime. 

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2. In operando cryo-STEM of pulse-induced charge density wave switching in TaS2

   https://doi.org/10.1038/s41467-023-44093-2  

   Hart, James L.; Siddique, Saif; Schnitzer, Noah; Funni, Stephen D.; Kourkoutis, Lena F.; Cha, Judy J. (December 2023, Nature Communications)

   Abstract The charge density wave material 1T-TaS₂exhibits a pulse-induced insulator-to-metal transition, which shows promise for next-generation electronics such as memristive memory and neuromorphic hardware. However, the rational design of TaS₂devices is hindered by a poor understanding of the switching mechanism, the pulse-induced phase, and the influence of material defects. Here, we operate a 2-terminal TaS₂device within a scanning transmission electron microscope at cryogenic temperature, and directly visualize the changing charge density wave structure with nanoscale spatial resolution and down to 300 μs temporal resolution. We show that the pulse-induced transition is driven by Joule heating, and that the pulse-induced state corresponds to the nearly commensurate and incommensurate charge density wave phases, depending on the applied voltage amplitude. With our in operando cryogenic electron microscopy experiments, we directly correlate the charge density wave structure with the device resistance, and show that dislocations significantly impact device performance. This work resolves fundamental questions of resistive switching in TaS₂devices, critical for engineering reliable and scalable TaS₂electronics. 

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3. Watermarked ReRAM: A Technique to Prevent Counterfeit Memory Chips

   https://doi.org/10.1145/3526241.3530341  

   Ferdaus, Farah; Bahar Talukder, Bashir Mohammad; Rahman, Md Tauhidur (June 2022, Proceedings of the Great Lakes Symposium on VLSI 2022)

   Electronic counterfeiting is a longstanding problem with adverse long-term effects for many sectors, remaining on the rise. This article presents a novel low-cost technique to embed watermarking in devices with resistive-RAM (ReRAM) by manipulating its analog physical characteristics through switching (set/reset) operation to prevent counterfeiting. We develop a system-level framework to control memory cells' physical properties for imprinting irreversible watermarks into commercial ReRAMs that will be retrieved by sensing the changes in cells' physical properties. Experimental results show that our proposed ReRAM watermarking is robust against temperature variation and acceptably fast with ~0.6bit/min of imprinting and ~15.625bits/s of retrieval rates. 

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4. Observation of current-induced switching in non-collinear antiferromagnetic IrMn3 by differential voltage measurements

   https://doi.org/10.1038/s41467-021-24237-y  

   Arpaci, Sevdenur; Lopez-Dominguez, Victor; Shi, Jiacheng; Sánchez-Tejerina, Luis; Garesci, Francesca; Wang, Chulin; Yan, Xueting; Sangwan, Vinod K.; Grayson, Matthew A.; Hersam, Mark C.; et al (December 2021, Nature Communications)

   Abstract There is accelerating interest in developing memory devices using antiferromagnetic (AFM) materials, motivated by the possibility for electrically controlling AFM order via spin-orbit torques, and its read-out via magnetoresistive effects. Recent studies have shown, however, that high current densities create non-magnetic contributions to resistive switching signals in AFM/heavy metal (AFM/HM) bilayers, complicating their interpretation. Here we introduce an experimental protocol to unambiguously distinguish current-induced magnetic and nonmagnetic switching signals in AFM/HM structures, and demonstrate it in IrMn 3 /Pt devices. A six-terminal double-cross device is constructed, with an IrMn 3 pillar placed on one cross. The differential voltage is measured between the two crosses with and without IrMn 3 after each switching attempt. For a wide range of current densities, reversible switching is observed only when write currents pass through the cross with the IrMn 3 pillar, eliminating any possibility of non-magnetic switching artifacts. Micromagnetic simulations support our findings, indicating a complex domain-mediated switching process. 

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5. Effects of Spent Coffee Grounds on Improvement of Resistive Switching Characteristics in Natural Rubber‐Based Memory

   https://doi.org/10.1002/smll.202504260  

   Awais, Muhammad; Othman, Nadras; Shafiq, Mohamad_Danial; Zhao, Feng; Cheong, Kuan_Yew (June 2025, Small)

   Abstract The recent upsurge in environmental awareness provokes the widespread usage of green materials in sustainable electronic applications. Herein, the effects of spent coffee grounds (SCGs) on natural rubber (NR)‐based resistive switching (RS) memory are systematically investigated. This study presents the fabrication of a metal‐insulator‐metal (MIM) structure using NR incorporated with SCGs (0 to 8 wt.%) as a memristive layer and sandwiched between electrodes. A significant improvement in the ON/OFF ratio from 10⁴for pure NR to 10⁷, read memory window increased from 2.03 to 2.45 V with improved stability even after 130 cycles of switching is achieved with the optimal concentration of SCGs (6 wt.%). The improved performance after the incorporation of SCGs is attributed to the introduction of key chemical functional groups (C═O, C═C) in the memristive film. By varying the viscosity of NR, bending of test structure, and voltage sweep rate, the effects of trap density and location on the RS performance are established. The RS mechanisms in high and low resistance states are dominated by space‐charge‐limited conduction and Ohm's law, respectively. This research manifests the potential of SCGs in improving the RS performance of bioorganic‐based memory devices. 

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