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Unfolding-based single-stage ac-dc converters offer benefits in terms of efficiency and power density due to the low-frequency operation of the Unfolder, resulting in negligible switching losses. However, the operation of the Unfolder results in time-varying dc voltages at the input of the subsequent dc-dc converter, complicating its soft-switching analysis. The complication is further enhanced due to the nonlinear nature of the output capacitance ( Coss ) of MOSFETs employed in the dc-dc converter. Furthermore, unlike two-stage topologies with a constant dc-link voltage, as seen in high-frequency grid-tied converters, grid voltage fluctuations also impact the dc input voltages of the dc-dc converter in unfolding-based systems. This work comprehensively analyzes the soft-switching phenomenon in the T-type primary bridge-based dc-dc converter used in unfolding-based topologies, considering all the aforementioned challenges. An energy-based methodology is proposed to determine the minimum zero-voltage switching (ZVS) current and ZVS time during various switching transitions of the T-type bridge. It is shown that the existing literature on the ZVS analysis of the T-type bridge-based resonant dc-dc converter, relying solely on capacitive energy considerations, substantially underestimates the required ZVS current values, with errors reaching up to 50%. The proposed analysis is verified through both simulation and hardware testing. The hardware testing is conducted on a 20-kW 3- ϕ unfolding-based ac-dc converter designed for high-power electric vehicle battery charging applications. The ZVS analysis is verified at various grid angles with the proposed analysis ensuring a complete ZVS operation of the ac-dc system throughout the grid cycle.
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This content will become publicly available on April 1, 2026
Optimized Timing Control for Leading-Edge Aligned Modulation of a T-Type Bridge in Unfolding-Based AC–DC Converters
T-type primary bridge-based resonant converters employed in unfolding-based single-stage ac–dc conversion systems commonly adopt a leading-edge aligned modulation strategy, as it facilitates zero-voltage switching (ZVS) throughout the grid cycle. However, the application of this modulation strategy can result in partial ZVS of the common-source mosfets within the T-type bridge. In this letter, we investigate the underlying reasoning of such partial ZVS, quantify the severity of the problem, and propose a mitigation solution. Specifically, an optimized leading-edge aligned modulation strategy is introduced, incorporating an intentional staggered time delay for the turn-off of the common-source mosfets during the leading edge. The proposed modulation strategy is validated through hardware testing on a 20-kW unfolding-based ac–dc conversion system.
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- Award ID(s):
- 2239169
- PAR ID:
- 10617218
- Publisher / Repository:
- IEEE Transactions on Power Electronics
- Date Published:
- Journal Name:
- IEEE Transactions on Power Electronics
- Volume:
- 40
- Issue:
- 4
- ISSN:
- 0885-8993
- Page Range / eLocation ID:
- 4716 to 4721
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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