An official website of the United States government
Spiking neural networks (SNNs) are powerful models of spatiotemporal computation and are well suited for deployment on resource-constrained edge devices and neuromorphic hardware due to their low power consumption. Leveraging attention mechanisms similar to those found in their artificial neural network counterparts, recently emerged spiking transformers have showcased promising performance and efficiency by capitalizing on the binary nature of spiking operations. Recognizing the current lack of dedicated hardware support for spiking transformers, this paper presents the first work on 3D spiking transformer hardware architecture and design methodology. We present an architecture and physical design co-optimization approach tailored specifically for spiking transformers. Through memory-on-logic and logic-on-logic stacking enabled by 3D integration, we demonstrate significant energy and delay improvements compared to conventional 2D CMOS integration.
more »
« less
A van der Waals interfacial junction transistor for reconfigurable fuzzy logic hardware
Edge devices face challenges when implementing deep neural networks due to constraints on their computational resources and power consumption. Fuzzy logic systems can potentially provide more efficient edge implementations due to their compactness and capacity to manage uncertain data. However, their hardware realization remains difficult, primarily because implementing reconfigurable membership function generators using conventional technologies requires high circuit complexity and power consumption. Here we report a multigate van der Waals interfacial junction transistor based on a molybdenum disulfide/graphene heterostructure that can generate tunable Gaussian-like and π-shaped membership functions. By integrating these generators with peripheral circuits, we create a reconfigurable fuzzy controller hardware capable of nonlinear system control. This fuzzy logic system can also be integrated with a few-layer convolution neural network to form a fuzzy neural network with enhanced performance in image segmentation.
more »
« less
- PAR ID:
- 10621522
- Publisher / Repository:
- Springer Nature
- Date Published:
- Journal Name:
- Nature Electronics
- Volume:
- 7
- Issue:
- 10
- ISSN:
- 2520-1131
- Page Range / eLocation ID:
- 876-884
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
More Like this
-
-
Images are often corrupted with noise. As a result, noise reduction is an important task in image processing. Common noise reduction techniques, such as mean or median filtering, lead to blurring of the edges in the image, while fuzzy filters are able to preserve the edge information. In this work, we implement an efficient hardware design for a well-known fuzzy noise reduction filter based on stochastic computing. The filter consists of two main stages: edge detection and fuzzy smoothing. The fuzzy difference, which is encoded as bit-streams, is used to detect edges. Then, fuzzy smoothing is done to average the pixel value based on eight directions. Our experimental results show a significant reduction in the hardware area and power consumption compared to the conventional binary implementation while preserving the quality of the results.more » « less
-
Modern cyber-physical systems often make use of heterogeneous systems-on-chip with reconfigurable logic to provide adequate computing power and flexible I/O. However, modeling, verifying, and implementing the computations spanning CPUs and reconfigurable logic are still challenging. The hardware and software components are often designed by different teams and at different levels of abstraction, making it hard to reason about the resulting computation. We propose to lift both hardware and software design to the same level of abstraction by using the Lingua Franca coordination language. Lingua Franca is based on a sparse synchronous model that allows modeling concurrency and timing while keeping a sequential model for the actual computation. We define hardware reactors as a subset of the reactor model of computation underlying Lingua Franca. We also present and evaluate reactor-chisel, a hardware runtime implementing the semantics of hardware reactors, and an extension to the Lingua Franca compiler enabling reactor-oriented hardware–software codesign.more » « less
-
Fuzzy logic controllers can handle complex systems by incorporating expert’s knowledge in the absence of formal mathematical models. Further, fuzzy logic controllers can effectively capture and accommodate uncertainties that are inherent in real-world controlled systems. On the other hand, Robot Operating System (ROS) has been widely used for many robotic applications due to its modular structure and efficient message-passing mechanisms for the integration of system’s components. For this reason, Robot Operating System is an ideal tool for developing software stacks for robotic applications. This paper develops a generic and configurable Robot Operating System package for the implementation of fuzzy logic controllers, particularly type-1 and interval type-2, which are based on either Mamdani or Takagi-Sugeno-Kang fuzzy inference mechanisms. This is achieved by employing a systematic object-oriented approach using the Unified Model Language (UML) to implement the fuzzy inference system as a single class that is composed of fuzzifier, inference, and defuzzifier classes. The deployment of the developed Robot Operating System package is demonstrated by implementing an interval type-2 fuzzy logic control of an Unmanned Aerial Vehicle (UAV).more » « less
-
Using binarized neural network (BNN) as an alternative to the conventional convolutional neural network is a promising candidate to answer the demand of using human brain-inspired in applications with limited hardware and power resources, such as biomedical devices, IoT edge sensors, and other battery-operated devices. Using nonvolatile memory elements like MTJ devices in a LiM-based architecture can eliminate the need to access and use external memory which can significantly reduce the power consumption and area overhead. In addition, by using adiabatic-based designs, a significant part of the consumed power can be recovered to the power source which leads to a huge reduction in power consumption which is vital in applications with limited power and hardware resources. In this paper by using nonvolatile MTJ devices in a LiM architecture and using adiabatic-based circuits, an XNOR/XOR synapse and neuron is proposed. The proposed design offers 97% improvement in comparison with its state-of-the-art counterparts in case of power consumption. Also, it achieves at least 7% lower area compared to other counterparts which makes the proposed design a promising candidate for hardware implementation of BNNs.more » « less
- Free Publicly Accessible Full Text
-
Accepted Manuscript1.0
- Journal Article:
- https://doi.org/10.1038/s41928-024-01256-3
