skip to main content
US FlagAn official website of the United States government
dot gov icon
Official websites use .gov
A .gov website belongs to an official government organization in the United States.
https lock icon
Secure .gov websites use HTTPS
A lock ( lock ) or https:// means you've safely connected to the .gov website. Share sensitive information only on official, secure websites.

Attention:

The NSF Public Access Repository (PAR) system and access will be unavailable from 10:00 PM ET on Friday, February 6 until 10:00 AM ET on Saturday, February 7 due to maintenance. We apologize for the inconvenience.


Title: Design Techniques for a Multi-Phase Injection-Based Eight-Phase 17-GHz Clock Generator for Multi-Phase Wireline Receivers
Clock generation for high-speed wireline receivers must provide multiple clock phases with high-resolution rotation. To address this, an 8-phase 17 GHz clock generation circuit with built-in 6b rotation is presented. Multi-phase injection is used to perform reference-side phase rotation to efficiently generate and rotate eight clock phases. The injection method is analyzed with a model to study the introduced nonlinearity, and the effect of the injection strength is discussed. Designed by using BAG3++ for layout-aware design optimization, the proposed circuit achieves 98 fs RMS jitter and a measured DNLpp and INLpp of 1.26 and 4.05 LSB respectively, while consuming 33 mW.  more » « less
Award ID(s):
2148021
PAR ID:
10630710
Author(s) / Creator(s):
;
Corporate Creator(s):
Editor(s):
NA
Publisher / Repository:
IEEE Transactions on Circuits and Systems I: Regular Papers ( Early Access )
Date Published:
Journal Name:
IEEE Transactions on Circuits and Systems I: Regular Papers
ISSN:
1549-8328
Page Range / eLocation ID:
1 to 13
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
More Like this
  1. A high frequency multi-phase clock generator circuit with a 6b phase rotator is presented for multi-phase wireline receivers. Multi-phase injection is used to efficiently generate and rotate 8 clock phases. Unlike prior rotator-based work, this work does not use time modulation, reducing the resulting deterministic jitter. A model is presented to study the nonlinearity introduced by the technique. The proposed 17 GHz circuit was implemented in the Intel 16 process and consumes 33 mW. The measured RMS jitter is $$\mathbf{9 8} \mathrm{fs}$$, and the measured DNLpp and INLpp are 1.26 and 4.05 LSB respectively. 
    more » « less
  2. Enhanced susceptibilities in ferroelectrics often arise near phase boundaries between competing ground states. While chemically-induced phase boundaries have enabled ultrahigh electrical and electromechanical responses in lead-based ferroelectrics, precise chemical tuning in lead-free alternatives, such as (K,Na)NbO3 thin films, remains challenging due to the high volatility of alkali metals. Here, we demonstrate strain-induced morphotropic phase boundary-like polymorphic nanodomain structures in chemically simple, lead-free, epitaxial NaNbO3 thin films. Combining ab initio simulations, thin-film epitaxy, scanning probe microscopy, synchrotron X-ray diffraction, and electron ptychography, we reveal a labyrinthine structure comprising coexisting monoclinic and bridging triclinic phases near a strain-induced phase boundary. The coexistence of energetically competing phases facilitates field-driven polarization rotation and phase transitions, giving rise to a multi-state polarization switching pathway and large enhancements in dielectric susceptibility and tunability across a broad frequency range. Our results open new possibilities for engineering lead-free thin films with enhanced functionalities for next-generation applications. 
    more » « less
  3. Abstract Coupled electronic oscillators have recently been explored as a compact, integrated circuit- and room temperature operation-compatible hardware platform to design Ising machines. However, such implementations presently require the injection of an externally generated second-harmonic signal to impose the phase bipartition among the oscillators. In this work, we experimentally demonstrate a new electronic autaptic oscillator (EAO) that uses engineered feedback to eliminate the need for the generation and injection of the external second harmonic signal to minimize the Ising Hamiltonian. Unlike conventional relaxation oscillators that typically decay with a single time constant, the feedback in the EAO is engineered to generate two decay time constants which effectively helps generate the second harmonic signal internally. Using this oscillator design, we show experimentally, that a system of capacitively coupled EAOs exhibits the desired bipartition in the oscillator phases without the need for any external second harmonic injection, and subsequently, demonstrate its application in solving the computationally hard Maximum Cut (MaxCut) problem. Our work not only establishes a new oscillator design aligned to the needs of the oscillator Ising machine but also advances the efforts to creating application specific analog computing platforms. 
    more » « less
  4. Estimating a quantum phase is a necessary task in a wide range of fields of quantum science. To accomplish this task, two well-known methods have been developed in distinct contexts, namely, Ramsey interferometry (RI) in atomic and molecular physics and quantum phase estimation (QPE) in quantum computing. We demonstrate that these canonical examples are instances of a larger class of phase estimation protocols, which we call reductive quantum phase estimation (RQPE) circuits. Here, we present an explicit algorithm that allows one to create an RQPE circuit. This circuit distinguishes an arbitrary set of phases with a smaller number of qubits and unitary applications, thereby solving a general class of quantum hypothesis testing to which RI and QPE belong. We further demonstrate a tradeoff between measurement precision and phase distinguishability, which allows one to tune the circuit to be optimal for a specific application. Published by the American Physical Society2024 
    more » « less
  5. null (Ed.)
    Digital phase-locked loops (DPLL) are finding new applications in highly demanding contexts such as frequency synthesis for millimeter-wave (mm-wave) communications and clock generation for ultra-high-speed wireline transceivers. In a typical DPLL, however, a time-to-digital converter (TDC) with fine time resolution, high linearity and high dynamic range is required to meet stringent noise and spur performance requirements, which negatively impacts the power consumption in a DPLL. A bang-bang phase-detector (BBPD) outperforms a multi-bit TDC in terms of its’ jitter-power tradeoff, but its’ highly non-linear phase detection characteristic limits the locking speed of the loop. This research explores the design and of a 60 GHz digital sub-sampling phase-locked loop that uses a BBPD loop for frequency tracking and a coarse TDC loop for fast frequency acquisition. A prototype of the DPLL is designed in a 28-nm CMOS technology with supporting evidence through extensive simulations. 
    more » « less