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1. Dual-Loop Frequency Synchronization and Load Regulation using a Discrete Time Model for a 7-Level Switched Capacitor WPT Rectifier

   https://doi.org/10.1109/COMPEL49091.2020.9265670  

   Cochran, Spencer; Costinett, Daniel (November 2020, 2020 IEEE 21st Workshop on Control and Modeling for Power Electronics (COMPEL))

   null (Ed.)

   In wireless power transfer (WPT) applications, the multi-level switched capacitor topology achieves significant advantages in terms of efficiency, system loading, THD, and output regulation. The topology requires dual-loop control in order to harness these benefits. First, a small signal discrete time model for the 7-level rectifier WPT system is developed. Then, a control loop is designed that enables the rectifier to regulate DC load voltage by varying its modulation scheme. Next, the WPT carrier frequency is sensed and a phase-locked loop is used in combination with the small signal power stage model to design a closed-loop controller that synchronizes frequency and regulates control phase through adjustments of the switching period. Finally, cross-coupling interactions between the two control loops are modeled, and stable dual-loop operation is shown. 

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2. Protecting analog circuits with parameter biasing obfuscation

   https://doi.org/10.1109/LATW.2017.7906739  

   Rao, Vaibhav Venugopal; Savidis, Ioannis (March 2017, 2017 IEEE Latin American Test Symposium (LATS))

   A methodology to secure analog intellectual property (IP) by obfuscating biasing conditions is presented in this paper. Previous research methodologies have focused on protecting digital IP from theft, overproduction, counterfeiting, and Trojan insertion. Analog IP has not been investigated as it does not share the same replicated structures and functionalities used for digital protection. The bias encryption techniques presented in this paper are implemented on a phase locked loop (PLL). The operating frequency of the PLL is masked in the range of 800 MHz to 2.2 GHz with a 40-bit encryption key. The probability of determining the correct key through brute force attack is 9.095×10-13. The overheads of encrypting the PLL include a 6.3% increase in active area, a 0.89% increase in power consumption, and a 5 dBc/Hz increase in phase noise. 

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3. Discrete Time Synchronization Modeling for Active Rectifiers in Wireless Power Transfer Systems

   https://doi.org/10.1109/COMPEL.2019.8769717  

   Cochran, Spencer; Costinett, Daniel (June 2019, IEEE Workshop on Control and Modeling for Power Electronics (COMPEL))

   Active rectifiers in wireless power transfer systems exhibit many benefits compared to diode rectifiers, including increased efficiency, controllable impedance, and regulation capability. To achieve these benefits, the receivers must synchronize their switching frequency to the transmitter to avoid sub-fundamental beat frequency oscillations. Without additional communication, the receiver must synchronize to locally-sensed signals, such as voltages and currents induced in the power stage by the transmitter. However, the waveforms in the receiver are dependent on both the transmitter and receiver operation, resulting in an internal feedback between sensing and synchronization which prohibits the use of traditional phase-locked-loop design techniques. In this digest, a discrete time state space model is developed and used to derive a small signal model of these interactions for the purpose of designing stable closed-loop synchronization control. A prototype 150 kHz wireless power transfer converter is used to experimentally validate the modeling, showcasing stable synchronization. 

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4. Realization of Enhanced Phase Locked Loop using Raspberry Pi and LabVIEW

   https://doi.org/10.1109/NAPS46351.2019.9000278  

   Kolla, Rama; Wang, Zhengyu; Miao, Zhixin; Fan, Lingling (October 2019, IEEE)

   Real-time data is gaining more importance in engineering. With archived data and the real-time data, utilities are making systems more robust by developing new methods for controlling and monitoring. Frequency information of the system is one of the key factors for better controlling and monitoring purpose. So acquiring real-time frequency information at a low cost is really important. Raspberry Pi based frequency data acquisition is one of the solutions to get data remotely. This paper discusses two main topics: (i) The complete procedure for acquiring the real-time data using Raspberry Pi, Multi-chip package 3008 and LabVIEW. (ii) Modeling of Enhanced Phase Locked Loop (PLL) and its integration with the data acquisition system for processing the real-time data to extract the frequency and amplitude information. 

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5. A Time-to-Voltage Converter With Miller-Impedance Technique for Single-Photon Arrival Time-to-Digital Conversions

   https://doi.org/10.1109/OJCAS.2025.3625587  

   Yang, Ruoman; Hsueh, Tzu-Chien (October 2025, IEEE Open Journal of Circuits and Systems)

   A low-power time-to-voltage converter (TVC) is composed of a reconfigurable current-mode integrator and a capacitive voltage holder specifically for random sampling-and-averaging (RSA) time-to-digital conversions (TDC) in time-correlated single-photon counting (TCSPC) systems. To accommodate the TVC circuit within each single-photon detection pixel for compact silicon-photonics integration, this paper exploits the Miller-impedance technique to demonstrate the leakage time-constant of the voltage holder being extended up to tens of milliseconds, which represents a more than 100× improvement in high-leakage 22-nm digital CMOS process technology, with only a 9-pF (36-µm × 36-µm) metal-finger hold capacitor and 120-µW power consumption. 

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