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Title: A 60-GHz Digital Sub-Sampling Integer-N Phase-Locked Loop
Digital phase-locked loops (DPLL) are finding new applications in highly demanding contexts such as frequency synthesis for millimeter-wave (mm-wave) communications and clock generation for ultra-high-speed wireline transceivers. In a typical DPLL, however, a time-to-digital converter (TDC) with fine time resolution, high linearity and high dynamic range is required to meet stringent noise and spur performance requirements, which negatively impacts the power consumption in a DPLL. A bang-bang phase-detector (BBPD) outperforms a multi-bit TDC in terms of its’ jitter-power tradeoff, but its’ highly non-linear phase detection characteristic limits the locking speed of the loop. This research explores the design and of a 60 GHz digital sub-sampling phase-locked loop that uses a BBPD loop for frequency tracking and a coarse TDC loop for fast frequency acquisition. A prototype of the DPLL is designed in a 28-nm CMOS technology with supporting evidence through extensive simulations.  more » « less
Award ID(s):
1823235
PAR ID:
10293905
Author(s) / Creator(s):
; ; ;
Date Published:
Journal Name:
2020 IEEE Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS)
Page Range / eLocation ID:
1 to 5
Format(s):
Medium: X
Sponsoring Org:
National Science Foundation
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