An official website of the United States government
Industry trends are moving toward increasing use of chiplets as a replacement for monolithic fabrication in many modern chips. Each chiplet is a separately-produced silicon die, and a system-on-chip (SoC) is created by packaging the chiplets together on a silicon interposer or bridge. Chiplets enable IP reuse, heterogeneousintegration, and better ability to leverage cost-appropriate process nodes. Yet, creating systems from separately produced components also brings security risks to consider, such as the possibility of die swapping, or susceptibility to interposer probing or tampering. In a zero-trust security posture, a chiplet should not blindly assume it is operating in a friendly environment.In this paper we propose a delay-based PUF for chiplets to verify system integrity. Our technique allows a single chiplet to initiate a protocol with its neighbors to measure unique variations in the propagation delays of incoming signals as part of an integrity check. We prototype our design on Xilinx Ultrascale+ FPGAs, which are constructed as multi-die systems on a silicon interposer, and which also emulate the general features of other industrial chiplet interfaces. We perform experiments on, and compare data from, dozens of Ultrascale+ FPGAs by making use of Amazon’s Elastic Compute Cloud (EC2) F1 instances as a testing platform. The PUF cells are shown to reject clock and temperature variation as common mode, and each cell produces approximately 5 ps of unique delay variation. For a design with 144 PUF cells, we measure the mean within-class and between-class distances to be 68.3 ps and 847.7 ps, respectively. The smallest between-class distance of 686.0 ps exceeds the largest within-class distance of 124.0 ps by more than 5x under nominal conditions, and the PUF is shown to be resilient to environmental changes. Our findings indicate the PUF can be used for authentication, and is potentially sensitive enough to detect picosecond-scale timing changes due to tampering.
more »
« less
This content will become publicly available on June 8, 2026
128-Channel Multi-Chip Acoustic Hologram Generator
An ASIC combines a numerically controlled oscillator with reconfigurable amplitude and phase control of 16 channels to synthesize acoustic holograms with a phased array of ultrasonic transmitters. Multiple chiplets operate synchronously to drive arbitrarily many channels. A scalable digital delay line technique, leveraging on-chip SRAM and single-bit noise-shaped bitstreams, realizes area-efficient, high-density, and high-resolution true-time-delay phase shifts. The prototype system employs 8 chiplets to drive a 128-element array for hologram generation.
more »
« less
- Award ID(s):
- 2153821
- PAR ID:
- 10635905
- Publisher / Repository:
- IEEE
- Date Published:
- ISBN:
- 978-4-86348-815-1
- Page Range / eLocation ID:
- 1 to 3
- Format(s):
- Medium: X
- Location:
- Kyoto, Japan
- Sponsoring Org:
- National Science Foundation
More Like this
-
-
Modern mmWave systems have limited scalability due to inflexibility in performing frequency multiplexing. All the frequency components in the signal are beamformed to one direction via pencil beams and cannot be streamed to other user directions. We present a new flexible mmWave system called mmFlexible, which enables flexible directional frequency multiplexing. In this system, different frequency components of the mmWave signal are beamformed in multiple arbitrary directions with the same pencil beam. Our system makes two key contributions: (1) We propose a novel mmWave front-end architecture, called a delay-phased array, that utilizes a variable delay and variable phase element to create the desired frequency-direction response. (2) We propose a novel algorithm called FSDA (Frequency-space to delay-antenna) to estimate delay and phase values for the real-time operation of the delay-phased array. Through evaluations using mmWave channel traces, we demonstrate that mmFlexible achieves a 60-150% reduction in worst-case latency compared to the baselines.more » « less
-
Heterogeneous chiplets have been proposed for accelerating high-performance computing tasks. Integrated inside one package, CPU and GPU chiplets can share a common interconnection network that can be implemented through the interposer. However, CPU and GPU applications have very different traffic patterns in general. Without effective management of the network resource, some chiplets can suffer significant performance degradation because the network bandwidth is taken away by communication-intensive applications. Therefore, techniques need to be developed to effectively manage the shared network resources. In a chiplet-based system, resource management needs to not only react in real-time but also be cost-efficient. In this work, we propose a reconfigurable network architecture, leveraging Kalman Filter to make accurate predictions on network resources needed by the applications and then adaptively change the resource allocation. Using our design, the network bandwidth can be fairly allocated to avoid starvation or performance degradation. Our evaluation results show that the proposed reconfigurable interconnection network can dynamically react to the changes in traffic demand of the chiplets and improve the system performance with low cost and design complexity.more » « less
-
This work presents a 4-channel, mm-scale, electrostatic and piezoelectric actuator driver that uses < 1μA total quiescent bias current and can drive actuator loads up to 120-330V at frequencies over 1kHz. The driver achieves over 99% current efficiency and can operate untethered with an integrated photovoltaic array driven by a collimated or diffuse optical power source. The circuit is tested with an off-chip boost circuit, generating over 1.5kV with 85% power efficiency at 45mW load. The system uses a simple 4-bit CMOS logic level interface with 100 kHz clock to actuate high voltage channels; on-chip photovoltaics also power the digital controller, and I/O bus.more » « less
-
In this paper, a novel 2D Nolen beamforming phased array with 3D scanning capability to achieve high channel capacity is presented for multiple-input multiple-output (MIMO) Internet-of-Things (IoT) applications. The proposed 2D beamforming phased array is designed by stacking a fundamental building block consisting of a 3 × 3 tunable Nolen matrix, which applies a small number of phase shifters with a small tunning range and reduces the complexity of the beam-steering control mechanism. Each 3 × 3 tunable Nolen matrix can achieve a full 360° range of progressive phase delay by exciting all three input ports, and nine individual radiation beams can be generated and continuously steered on azimuth and elevation planes by stacking up three tunable Nolen matrix in horizontal and three in vertical to maximize signal-to-noise ratio (SNR) in the corresponding spatial directions. To validate the proposed design, the simulations have been conducted on the circuit network and assessed in a fading channel environment. The simulation results agree well with the theoretical analysis, which demonstrates the capability of the proposed 2D Nolen beamforming phased array to realize high channel capacity in MIMO-enabled IoT communications.more » « less
