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In this paper, a monotonic power side-channel attack (PSA) is proposed to analyze the security vulnerabilities of flash analog-to-digital converters (ADC), where the digital output of a flash ADC is determined by characterizing the monotonic relationship between the traces of the power consumed and the applied input signals. A novel technique that leverages clock phase division is proposed to secure the power side channel information of a 4-bit flash ADC. The proposed technique adds randomness to decorrelate the input signal from the given power trace as the execution phase of each comparator depends on a thermometer code computed from the previous seven clock cycles. The monotonic PSA is executed on both a secured and unsecured ADC, with results indicating 1.9 bits of information leakage from an unprotected ADC and no data leakage from a protected ADC as the bit-wise accuracy is approximately 50% when secured. The monotonic PSA is more effective at attacking a flash ADC architecture than either a convolutional neural network based PSA or a correlation template PSA. The secured ADC core occupies approximately 2% more area than a non-secure ADC in a 65 nm process, and provides a sampling frequency of up to 500 MHz at a supply voltage of 1.2 V. Index Terms—power side-channel, ADC,
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This content will become publicly available on August 25, 2026
A Proxy ADC Framework for Side-Channel Secure ADC Analysis
In the rapidly evolving world of hardware security, developing metrics for evaluating the security improvements of hardware designs is important. This work examines the prevailing threat model for secure analog-to-digital converter (ADC) architectures and explains how signal-to-noise ratio (SNR), root-mean-square error (RMSE), and bit-wise accuracy (BWA) are used to evaluate security improvements. The existing metrics are mathematically related through the proposed Proxy ADC framework. The proposed SNR-RMSE and BWA-RMSE relationships are validated using a power side-channel attack on a commercial ADC. The SNR-RMSE relationship achieves an average percent error of 1.69% across four trials, while the BWA-RMSE relationship achieves an average of 7.97%. Using results from past secure ADC works allows for additional demonstrations of the relationships. These relationships can estimate accuracy in a realistic attack scenario where ADC outputs cannot be measured to verify the evaluation, and recontextualize the metrics of standard ADC design for hardware security. Furthermore, the Proxy ADC framework allows for comparison of tradeoffs between designs’ security and efficiency, revealing trends to leverage for future secure architectures.
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- Award ID(s):
- 2321255
- PAR ID:
- 10657282
- Editor(s):
- Shen, Y
- Publisher / Repository:
- IEEE
- Date Published:
- Journal Name:
- IEEE Open Journal of Circuits and Systems
- Volume:
- 6
- ISSN:
- 2644-1225
- Page Range / eLocation ID:
- 401 to 413
- Subject(s) / Keyword(s):
- hardware security, analog-to-digital converter, side-channel attack, successive approximation register
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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