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Following the rapid progress in the post-quantum cryptography (PQC) field that many efforts have been gradually switched to the hardware implementation side, this paper presents a novel systolic accelerator for polynomial multiplication within two lattice-based PQC algorithms, key encapsulation mechanism (KEM) Saber and binary Ring-Learning-with-Errors (BRLWE)-based encryption scheme. Based on the observation that polynomial multiplication over ring is the key arithmetic operation for the two PQC schemes, we have proposed a novel systolic accelerator for the targeted polynomial multiplications (applicable to two PQC schemes). Mathematical formulation is given to illustrate the proposed algorithmic operation for both schemes. Then, the proposed systolic accelerator is presented. Finally, field-programmable gate array (FPGA) implementation results have been provided to confirm the efficiency of the proposed systolic accelerator under two schemes. The proposed accelerator is highly efficient, and the following work may focus on cryptoprocessor design and side-channel attacks.
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RECAPHE: REconfigurable Polynomial Modular Computation Architectures for Unified PQC and HE Schemes
Post-Quantum Cryptography (PQC) and Homomorphic Encryption (HE) are emerging security primitives that strengthen data protection against adversaries equipped with quantum computing capabilities. Although PQC and HE rely on similar underlying arithmetic operations, their hardware implementations are typically developed independently due to differences in key parameters such as polynomial length and modulus bit-width. This work presents a unified lattice-based polynomial modular accelerator that efficiently supports both PQC and HE primitives, bridging these two domains toward future secure computing architectures. The proposed design introduces highly reconfigurable modular computation units that enable low-overhead runtime configuration across the parameter ranges commonly used in PQC and HE schemes. This unified architecture eliminates the need for separate domain-specific accelerators by reusing shared computation structures and workload patterns across both cryptographic schemes.
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- PAR ID:
- 10674498
- Publisher / Repository:
- IEEE
- Date Published:
- ISBN:
- 979-8-3315-8745-1
- Page Range / eLocation ID:
- 1288 to 1292
- Subject(s) / Keyword(s):
- Lattice-based cryptography Homomorphic encryption Post quantum cryptography FPGA Reconfigurable computing
- Format(s):
- Medium: X
- Sponsoring Org:
- National Science Foundation
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- Free Publicly Accessible Full Text
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Accepted Manuscript
- Conference Paper:
- https://doi.org/10.1109/IEEECONF67917.2025.11443610
