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Creators/Authors contains: "Chowdhury, Tanmoy"

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  1. ; ; (, IEEE Transactions on Knowledge and Data Engineering)
    Free, publicly-accessible full text available December 1, 2025
  2. ; ; ; ; ; (, Neural Networks)
    Free, publicly-accessible full text available December 1, 2025
  3. ; ; ; (, Society for Industrial and Applied Mathematics)
    Accepted Manuscript Full Text Available
  4. ; ; ; ; (, AISTAT 2024)
    Free, publicly-accessible full text available May 25, 2025
  5. ; ; ; ; (, AISTAT 2024)
    Accepted Manuscript Full Text Available
  6. ; ; ; ; ; ; ; ; ; ; et al (, GLSVLSI '22: Proceedings of the Great Lakes Symposium on VLSI)
    This paper presents RAPTA, a customized Representation-learning Architecture for automation of feature engineering and predicting the result of Path-based Timing-Analysis early in the physical design cycle. RAPTA offers multiple advantages compared to prior work: 1) It has superior accuracy with errors std ranges 3.9ps~16.05ps in 32nm technology. 2) RAPTA's architecture does not change with feature-set size, 3) RAPTA does not require manual input feature engineering. To the best of our knowledge, this is the first work, in which Bidirectional Long Short-Term Memory (Bi-LSTM) representation learning is used to digest raw information for feature engineering, where generation of latent features and Multilayer Perceptron (MLP) based regression for timing prediction can be trained end-to-end. 
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