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Mixture-of-Experts (MoE) architectures achieve efficient LLM inference through sparse activation, but this transforms static computation graphs into dynamic, token-dependent control flows that create new hardware security vulnerabilities. We present a cross-layer fault injection framework targeting the control-flow primitives of MoE execution. Using Qwen1.5-MoE as a case study, we show that the gating mechanism is a structural single-point-of-failure: a single bit-flip in the router logits collapses reasoning performance to 0%, while equivalent faults in dense models produce only minor numerical noise. We validate two complementary defenses: (1) gate-level Triple Modular Redundancy (TMR) that triplicates routing logic and applies majority voting, recovering discriminative accuracy (BBQ: 41%, toward baseline 43%) with 0.04% parameter overhead; and (2) a Validity Checker fallback that detects anomalous logits and routes tokens through the shared expert only, preventing catastrophic collapse (BBQ: 25% → 47%) at 44% reduced latency. 

RTL generation is more than code synthesis. Designs must be syntactically valid, synthesizable, correct, hardware-efficient. SOTA evaluations stop at functional correctness and do not measure synthesis and implementation quality. This paper evaluates 32 language models on 202 Verilog tasks from VerilogEval and RTLLM using the Hardware Quality Index (HQI) that combines post-synthesis area, delay, and warnings related to expert references in a Nangate45 45 nm flow. Three performance regimes emerge: 14 frontier models achieve HQI > 66, led by Gemini-3-Pro at 87.5% coverage and 85.1 HQI; 15 models cluster 43–66 HQI; 3 are below 43. Gap between best-of-five capability and single-attempt quality spans 3.7–22.1 HQI points, limiting integration into agentic pipelines. A taxonomy of 195 synthesis failures reveals systematic divergence: proprietary models fail late through elaboration errors and synthesis timeout; open models fail early often due to missing module wrappers and non-synthesizable constructs, a pattern consistent with training corpora skewed toward simulation over synthesis-grade RTL. 

Integrated circuit design is a highly complex and time-consuming process. Leveraging large language models (LLMs) for automating hardware design generation is receiving increasing attention. A prominent challenge is that the inherent structure of the text is overlooked during the training process. Existing efforts focus on supervised fine-tuning LLMs to acquire specialized knowledge in hardware design, without considering the conflict between LLMs' linear data processing and the structural nature inherent in hardware design. In this work, we propose a novel LLM-based reinforcement learning (RL) framework that integrates Abstract Syntax Trees (ASTs) and Data Flow Graphs (DFGs). Our approach enhances the accuracy of generated hardware code by capturing the syntactic and semantic structures of hardware designs. Experimental results show that the SFT-RL model integrated with Text, AST, and DFG achieves notable improvements: a 12.57% increase on VerilogEval-Human and a 5.49% increase on VerilogEval-Machine, outperforming GPT-4; a 14.29% improvement on RTLLM, approaching GPT-4. 

The increasing complexity of integrated circuit design requires customizing Power, Performance, and Area (PPA) metrics according to different application demands. However, most engineers cannot anticipate requirements early in the design process, often discovering mismatches only after synthesis, necessitating iterative optimization or redesign. Some works have shown the promising capabilities of large language models (LLMs) in hardware design generation tasks, but they fail to tackle the PPA trade-off problem. In this work, we propose an LLM-based reinforcement learning framework, PPA-RTL, aiming to introduce LLMs as a cutting-edge automation tool by directly incorporating post-synthesis metrics PPA into the hardware design generation phase. We design PPA metrics as reward feedback to guide the model in producing designs aligned with specific optimization objectives across various scenarios. The experimental results demonstrate that PPA-RTL models, optimized for Power, Performance, Area, or their various combinations, significantly improve in achieving the desired trade-offs, making PPA-RTL applicable to a variety of application scenarios and project constraints.