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Creators/Authors contains: "Gupta, Subhanshu"

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  1. ; ; ; ; ; ( , IEEE)
    Free, publicly-accessible full text available June 16, 2025
  2. ; ; ; ; ; ; ( , IEEE)
    Millimeter-wave (mmWave) systems require a large number of antennas, which makes the beam training challenging and time-consuming for conventional phased arrays. Recently, a true-time-delay (TTD) array-based beam training algorithm has been shown as an effective solution to overcome the training overhead in large arrays. In this paper, we present a custombuilt over-the-air (OTA) testbed to study the effects of hardware impairments on the TTD-based beam training and verify its feasibility in a real system. We proposed an orthogonal matching pursuit (OMP) based reconstruction algorithm along with a phase calibration dictionary to combat nonidealities such as strong frequency selectivity and phase misalignment in the received raw IQ signal. Post-processing results showed that with the nonideality effects properly handled, the 3D TTD beam training algorithm can achieve high AOA estimation accuracy. 
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    Free, publicly-accessible full text available June 9, 2025
  3. ; ; ; ( , IEEE Journal of Solid-State Circuits)
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  4. ; ; ; ( , IEEE Transactions on Circuits and Systems II: Express Briefs)
    Full Text Available 
  5. ; ; ; ; ; ; ; ; ; ( , IEEE Journal of Solid-State Circuits)
    Pavan Hanumolu, Kenichi Okada (Ed.)
    Full Text Available 
  6. ; ; ; ; ; ; ( , IEEE Radio Frequency Integrated Circuits Symposium)
    In the baseband time delay (TD) elements used for delay compensation in discrete-time beamformers, phase interpolator (PI) plays a crucial role as the resolution of the PI defines the delay resolution of the TD. In this paper, we present a process and temperature invariant high-resolution and highly linear low-power PI. The proposed PI uses current integration which generates an adaptable constant slope-and-swing ramp signal to achieve low power. By switched-capacitor bias generation, the PI linearity is enhanced with 0.2 LSB DNL and 0.3 LSB INL, respectively. The 7-bit PI is realized in 65nm CMOS technology can generate the full range delay with a resolution of 8psec with the input of 1GHz. The PI consumes a power of 345μW and occupies an active area of 0.021mm2. Keywords—Ramp-rate tracking, constant slope-and-swing, phase interpolator, ramp-based, baseband time delay 
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    Accepted Manuscript Full Text Available
  7. ; ; ; ; ; ; ( , 2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC))
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  8. ; ; ; ; ; ; ( , IEEE Transactions on Circuits and Systems II: Express Briefs)
    Full Text Available 
  9. ; ( , IEEE Journal of Solid-State Circuits)
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  10. ; ; ; ; ; ; ; ; ( , IEEE European Solid-State Circuits Conference (ESSCIRC))
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