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Abstract A synaptic memristor using 2D ferroelectric junctions is a promising candidate for future neuromorphic computing with ultra‐low power consumption, parallel computing, and adaptive scalable computing technologies. However, its utilization is restricted due to the limited operational voltage memory window and low on/off current (I_ON/OFF) ratio of the memristor devices. Here, it is demonstrated that synaptic operations of 2D In₂Se₃ferroelectric junctions in a planar memristor architecture can reach a voltage memory window as high as 16 V (±8 V) and I_ON/OFFratio of 10⁸, significantly higher than the current literature values. The power consumption is 10⁻⁵ W at the on state, demonstrating low power usage while maintaining a large I_ON/OFFratio of 10⁸compared to other ferroelectric devices. Moreover, the developed ferroelectric junction mimicked synaptic plasticity through pulses in the pre‐synapse. The nonlinearity factors are obtained 1.25 for LTP, −0.25 for LTD, respectively. The single‐layer perceptron (SLP) and convolutional neural network (CNN) on‐chip training results in an accuracy of up to 90%, compared to the 91% in an ideal synapse device. Furthermore, the incorporation of a 3 nm thick SiO₂interface between the α‐In₂Se₃and the Au electrode resulted in ultrahigh performance among other 2D ferroelectric junction devices to date. 

Abstract 2D memristors have demonstrated attractive resistive switching characteristics recently but also suffer from the reliability issue, which limits practical applications. Previous efforts on 2D memristors have primarily focused on exploring new material systems, while damage from the metallization step remains a practical concern for the reliability of 2D memristors. Here, the impact of metallization conditions and the thickness of MoS₂films on the reliability and other device metrics of MoS₂‐based memristors is carefully studied. The statistical electrical measurements show that the reliability can be improved to 92% for yield and improved by ≈16× for average DC cycling endurance in the devices by reducing the top electrode (TE) deposition rate and increasing the thickness of MoS₂films. Intriguing convergence of switching voltages and resistance ratio is revealed by the statistical analysis of experimental switching cycles. An “effective switching layer” model compatible with both monolayer and few‐layer MoS₂, is proposed to understand the reliability improvement related to the optimization of fabrication configuration and the convergence of switching metrics. The Monte Carlo simulations help illustrate the underlying physics of endurance failure associated with cluster formation and provide additional insight into endurance improvement with device fabrication optimization.