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Managing the thermal behavior of GaN devices under test (DUT) poses significant challenges during accelerated thermal cycling (ATC) tests, particularly due to the compact packaging of small GaN devices (e.g., QFN package) and the sharp rise in the device's RDSon at high junction temperatures. This paper presents a framework for analyzing and modeling the thermal response performance of the ATC test setup and evaluating the impact of non-linear dissipated power on the GaN DUTs. It outlines the limitations of conventional thermal sensors in accurately estimating the DUT's junction temperature through case temperature measurements under ATC conditions. The analysis and modeling of the experimental junction temperature response function shows about 4 s time constant in the measurements using a thermistor placed near the DUT, highlighting the GaN DUT's susceptibility to thermal runaway under ATC conditions (Tj−max > 125 °C), where the thermal time constant significantly exceeds the DUT's thermal transient time. Consequently, an on-state resistance (RDSon)-based Tj estimation method is employed to monitor the Tj and control the thermal cycling window boundaries effectively. Experimental investigations of several e-mode GaN HEMTs under different ATC windows are conducted to validate the ATC testing framework. Moreover, the temperature coefficient of on-state resistance (α) is characterized and quantified - considering fully packaged individual GaN DUTs’ mechanical and electrical degradation mechanisms. 

This work introduces a machine learning approach for developing Digital Twins (DTs) for DC-DC converters, focusing on in-situ implementation in real-world operational conditions. A system based on a boost converter has been developed in MATLAB Simulink. To mirror real-world scenarios, commercial datasheets along with a range of input parameters, health degradation elements, temperature influence, and random noises have been considered. The study employs Multi-Layer Perceptron (MLP), Convolutional Neural Network (CNN), and Recurrent Neural Network (RNN) for predicting critical circuit responses of the boost converter, including inductor current, output voltage, and efficiency. Investigations show that MLP performs relatively poorly in the presence of noise. The CNN and RNN outperform the MLP under various noise levels, with the RNN exhibiting the best performance. This work advances DTs technology in power electronics, aiming to improve converter system optimization and enable predictive maintenance. 

DC microgrids incorporate several converters for distributed energy resources connected to different passive and active loads. The complex interactions between the converters and components and their potential failures can significantly affect the grids' resilience and health; hence, they must be continually assessed and monitored. This paper presents a machine learning-assisted prognostic health monitoring (PHM) and diagnosis approach, enabling progressive interactions between the converters at multiple nodes to dynamically examine the grid's (or micro-grid's) health in real time. By measuring the resulting impedance at the power converters' terminals at various grid nodes, a neural network-based classifier helps detect the grid's health condition and identify the potential fault-prone zones, along with the type and location of the fault type in the grid topology. For a faulty grid, a Naive Bayes and a support vector machine (SVM)-based classifiers are used to locate and identify the faulty type, respectively. A separate neural network-based regression model predicts the source power delivered and the loads at different terminals in a healthy grid network. The proposed concepts are supported by detailed analysis and simulation results in a simple four-terminal DC microgrid topology and a standard IEEE 5 Bus system. 

This paper presents an improved on-state resistance (RDSon) measurement scheme for high and low-side GaN FETs, which is critical for reliable and precise assessment of GaN HEMT power devices’ lifetime and degradation patterns. The proposed circuit is based on an active voltage clamp using Si MOSFET and Schottky and Zener diodes. The proposed circuit features lower parasitic inductances and capacitances by replacing the Si MOSFET with e-mode GaN FET. This modification contributed to much lower ringing and spikes in the voltage and current waveform of both the measurement FET and the DUT. The absence of an embedded body diode in the GaN device in the measurement circuit allows zero reverse recovery operation, making it more viable in high-frequency power converters. This study also provides a detailed design analysis of a bootstrap GaN-based on-state voltage (VDSon) sensing scheme for high-side FETs, useful in multiple converter configurations for in-situ devices’ health monitoring and conditioning. Simulation and experimental results validate the performance and features of the proposed concepts.