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Creators/Authors contains: "Li, Jinfeng"

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  1. This paper proposes a low-latency FPGA implemen-tation for Turbo equalization to combat very long multipathfading channels where the Intersymbol-interference (ISI) channellength is on the order of 100 taps. Turbo equalization is essentialfor such severe multipath channels, but exhibits very large latencyand high computational complexity due to its sequential anditerative data processing on large-scale matrix arithmetic. Thispaper proposes an FPGA acceleration architecture to exploitthe Hermitian symmetric property of the channel Gram matrixand convolutional nature of Sequential Interference Cancellation(SIC), and successfully implements a linear Turbo equalizerof 100 taps on a Xilinx Zynq UltraScale+ MPSoC ZCU102Evaluation Kit. The architecture is able to support two turboiterations for a 1024-symbol block size and achieve 200 kilo-symbols-per-second (ksps) transmission rate.
  2. JANUS is a physical layer communication standard for underwater acoustic communications published by North Atlantic Treaty Organization (NATO) in 2017. Instead of the nominal frequency band of 9440 – 13600 Hz specified in the standard, we adopt the JANUS packet for a high frequency band spanning from 96 kHz to 134 kHz. We also add cargo packets in the same frequency band using JANUS fast mode with a symbol rate of 23 ksps. Experiments were conducted in a swimming pool and the JANUS 3.0.5 Matlab version of the example receiver program was used to process the JANUS packets. We found that the example receiver program uses many fix(), round() and floor() functions which lead to synchronization errors. After modifying the simple rx code and fixing the error, our JANUS decoding results show that the adopted JANUS fast mode successfully achieves carrier and frame synchronization in all cases despite some bit errors remaining in the JANUS packet in severe multipath scenarios.