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Title: Hardware Implementation of Single-carrier Time-domain Turbo Equalization for Severe Multipath Acoustic Communication Channels
This paper proposes a low-latency FPGA implemen-tation for Turbo equalization to combat very long multipathfading channels where the Intersymbol-interference (ISI) channellength is on the order of 100 taps. Turbo equalization is essentialfor such severe multipath channels, but exhibits very large latencyand high computational complexity due to its sequential anditerative data processing on large-scale matrix arithmetic. Thispaper proposes an FPGA acceleration architecture to exploitthe Hermitian symmetric property of the channel Gram matrixand convolutional nature of Sequential Interference Cancellation(SIC), and successfully implements a linear Turbo equalizerof 100 taps on a Xilinx Zynq UltraScale+ MPSoC ZCU102Evaluation Kit. The architecture is able to support two turboiterations for a 1024-symbol block size and achieve 200 kilo-symbols-per-second (ksps) transmission rate.
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