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Predicting the minimum operating voltage Vmin of chips stands as a crucial technique in enhancing the speed and reliability of manufacturing testing flow. However, existing Vmin prediction methods often overlook various sources of variations in both training and deployment phases. Notably, overlooking wafer zone-to-zone (intra-wafer) variations and wafer-to-wafer (inter-wafer) variations diminishes the accuracy, data efficiency, and reliability of Vmin predictors. To address this challenge, we propose Restricted Bias Alignment (RBA), a novel data-efficient Vmin prediction framework that introduces a variation alignment technique to simultaneously estimate inter- and intra-wafer variations. Furthermore, we propose utilizing class probe data to model inter-wafer variations for the first time. 

3D-printed microdevices have become increasingly important to the advancement of point-of-care (POC) immunoassays. Despite its great potential, using 3D-printed surfaces on the solid support for immunorecognition has been limited due to the non-ideal adsorption properties for many photocurable resins. In this work, we report a simple surface modification protocol that works for diverse commercial photocurable resins, improving ELISAs performed directly on 3D-printed devices. This surface modification strategy involves surface activation via air plasma followed by the one-step incubation of GLYMO-labeled streptavidin. We successfully immobilized biotinylated anti-activin A antibodies on the 3D-printed surfaces and performed the complete ELISA protocol on the 3D-printed surfaces. We demonstrated that this protocol achieved an improved performance over passive adsorption for ELISAs. The present method is also compatible with diverse commercial resins and works with both microwells and microchannels. Finally, this method demonstrated a comparable limit of detection to the ELISA performed using commercial microwells. We believe the simplicity and broad compatibility of the present surface modification strategy will facilitate the development of 3D-printed POC ELISA devices. 

The increasing complexity of electronic systems in autonomous electric vehicles necessitates robust methods for forecasting the degradation of critical components such as printed circuit boards (PCBs). Various time series forecasting methods have been investigated to predict in-situ resistance degradation under vibration loads. However, these methods failed to capture the degradation trend under strong measurement noise. This paper introduces Monotonic Segmented Linear Regression (MSLR), a novel approach designed to capture monotonic degradation trends in time series data under significant measurement noise. By incorporating monotonic constraints, MSLR effectively models the non-decreasing behavior characteristic of degradation processes. To further enhance reliability of the prediction, we integrate Adaptive Conformal Inference (ACI) with MSLR, enabling the estimation of statistically valid upper bounds for resistance degradation with high confidence. Extensive experiments demonstrate that MSLR outperforms state-of-the-art time series forecasting baselines on real-world PCB degradation datasets. 

Self-Supervised Learning (SSL) has become a prominent approach for acquiring visual representations across various tasks, yet its application in fine-grained visual recognition (FGVR) is challenged by the intricate task of distinguishing subtle differences between categories. To overcome this, we introduce an novel strategy that boosts SSL's ability to extract critical discriminative features vital for FGVR. This approach creates synthesized data pairs to guide the model to focus on discriminative features critical for FGVR during SSL. We start by identifying non-discriminative features using two main criteria: features with low variance that fail to effectively separate data and those deemed less important by Grad-CAM induced from the SSL loss. We then introduce perturbations to these non-discriminative features while preserving discriminative ones. A decoder is employed to reconstruct images from both perturbed and original feature vectors to create data pairs. An encoder is trained on such generated data pairs to become invariant to variations in non-discriminative dimensions while focusing on discriminative features, thereby improving the model's performance in FGVR tasks. We demonstrate the promising FGVR performance of the proposed approach through extensive evaluation on a wide variety of datasets. 

Analog circuit design requires substantial human expertise and involvement, which is a significant roadblock to design productivity. Bayesian Optimization (BO), a popular machine-learning-based optimization strategy, has been leveraged to automate analog design given its applicability across various circuit topologies and technologies. Traditional BO methods employ black-box Gaussian Process surrogate models and optimized labeled data queries to find optimization solutions by trading off between exploration and exploitation. However, the search for the optimal design solution in BO can be expensive from both a computational and data usage point of view, particularly for high-dimensional optimization problems. This paper presents ADO-LLM, the first work integrating large language models (LLMs) with Bayesian Optimization for analog design optimization. ADO-LLM leverages the LLM’s ability to infuse domain knowledge to rapidly generate viable design points to remedy BO's inefficiency in finding high-value design areas specifically under the limited design space coverage of the BO's probabilistic surrogate model. In the meantime, sampling of design points evaluated in the iterative BO process provides quality demonstrations for the LLM to generate high-quality design points while leveraging infused broad design knowledge. Furthermore, the diversity brought by BO's exploration enriches the contextual understanding of the LLM and allows it to more broadly search in the design space and prevent repetitive and redundant suggestions. We evaluate the proposed framework on two different types of analog circuits and demonstrate notable improvements in design efficiency and effectiveness. 

Spiking neural networks (SNNs) are powerful models of spatiotemporal computation and are well suited for deployment on resource-constrained edge devices and neuromorphic hardware due to their low power consumption. Leveraging attention mechanisms similar to those found in their artificial neural network counterparts, recently emerged spiking transformers have showcased promising performance and efficiency by capitalizing on the binary nature of spiking operations. Recognizing the current lack of dedicated hardware support for spiking transformers, this paper presents the first work on 3D spiking transformer hardware architecture and design methodology. We present an architecture and physical design co-optimization approach tailored specifically for spiking transformers. Through memory-on-logic and logic-on-logic stacking enabled by 3D integration, we demonstrate significant energy and delay improvements compared to conventional 2D CMOS integration. 

Methane (CH4) oxidation is an important reaction to reduce the greenhouse effect caused by incomplete combustion of CH4. Here, we explored the mechanism of CH4 oxidation catalyzed by CeO2 and Ni-doped CeO2, focusing on the redox properties of these catalyst surfaces, using density functional theory (DFT). We found that the barriers for CH4* activation and H2O* formation are correlated with the surface redox capacity, which is enhanced by Ni doping. Furthermore, the complete reaction mechanism is explored by DFT calculations and microkinetic simulations on bare and Ni-doped CeO2 surfaces. Our calculations suggest that the doping of Ni leads to a much higher overall reactivity, due to a balance between the CH4* activation and H2O* formation steps. These results provide insights into the CH4 oxidation mechanism and the intrinsic relationship between redox properties and the activity of CeO2 surfaces. 

Spiking Neural Networks (SNNs) are brain-inspired computing models with event-driven based low-power operations and unique temporal dynamics. However, spatial and temporal dynamics in SNNs pose a significant overhead in accelerating neural computations and limit the computing capabilities of neuromorphic accelerators. Especially, unstructured sparsity emergent in both space and time, i.e., across neurons and time points, and iterative computations across time points cause a primary bottleneck in data movement. In this work, we propose a novel technique and architecture that allow the exploitation of temporal information compression with structured sparsity and parallelism across time, and significantly improves data movement on a systolic array. We split a full range of temporal domain into several time windows (TWs) where a TW packs multiple time points, and encode the temporal information in each TW with Split-Time Temporal coding (STT) by limiting the number of spikes within a TW up to one. STT enables sparsification and structurization of irregular firing activities and dramatically reduces computational overhead while delivering competitive classification accuracy without a huge drop. To further improve the data reuse, we propose an Integration Through Time (ITT) technique that processes integration steps across different TWs in parallel with a systolic array. The proposed architecture with STT and ITT offers an application-independent solution for spike-based models across various types of layers and networks. The proposed architecture delivers 97X latency and 78X energy efficiency improvements on average over a conventional SNN baseline on different benchmarks.