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Today's hundred-qubit quantum computers require a dramatic scale up to millions of qubits to become practical for solving real-world problems. Although a variety of qubit technologies have been demonstrated, scalability remains a major hurdle. Superconducting (SC) qubits are one of the most mature and promising technologies to overcome this challenge. However, these qubits reside in a millikelvin cryogenic dilution fridge, isolating them from thermal and electrical noise. They are controlled by a rack-full of external electronics through extremely complex wiring and cables. Although thousands of qubits can be fabricated on a single chip and cooled down to millikelvin temperatures, scaling up the control and readout electronics remains an elusive goal. This is mainly due to the limited available cooling power in cryogenic systems constraining the wiring capacity and cabling heat load management. In this article, we focus on scaling up the number of XY-control lines by using cryogenic RF-photonic links. This is one of the major roadblocks to build a thousand qubit superconducting QC. We will first review and study the challenges of state-of-the-art proposed approaches, including cryogenic CMOS and deep-cryogenic photonic methods, to scale up the control interface for SC qubit systems. We will discuss their limitations due to the active power dissipation and passive heat leakage in detail. By analytically modeling the noise sources and thermal budget limits, we will show that our solution can achieve a scale up to a thousand of qubits. Our proposed method can be seamlessly implemented using advanced silicon photonic processes, and the number of required optical fibers can be further reduced by using wavelength division multiplexing (WDM). 

This paper presents \textit{OFHE}, an electro-optical accelerator designed to process Discretized TFHE (DTFHE) operations, which encrypt multi-bit messages and support homomorphic multiplications, lookup table operations and full-domain functional bootstrappings. While DTFHE is more efficient and versatile than other fully homomorphic encryption schemes, it requires 32-, 64-, and 128-bit polynomial multiplications, which can be time-consuming. Existing TFHE accelerators are not easily upgradable to support DTFHE operations due to limited datapaths, a lack of datapath bit-width reconfigurability, and power inefficiencies when processing FFT and inverse FFT (IFFT) kernels. Compared to prior TFHE accelerators, OFHE addresses these challenges by improving the DTFHE operation latency by 8.7\%, the DTFHE operation throughput by $$57\%$$, and the DTFHE operation throughput per Watt by $$94\%$$.