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Abstract Previous Ku -band (15 GHz) imaging with data obtained from the Very Long Baseline Array (VLBA) had shown two compact, subparsec components at the location of a presumed kiloparsec-scale radio core in Seyfert galaxy NGC 7674. It was then presumed that these two unresolved and compact components were dual radio cores corresponding to two supermassive black holes (SMBHs) accreting surrounding gas and launching radio-bright relativistic jets. However, utilizing the original VLBA data set used to claim the detection of a binary SMBH, in addition to later multiepoch/multifrequency data sets obtained from both the VLBA and the European very long baseline interferometry (VLBI) network, we find no evidence to support the presence of a binary SMBH. We place stringent upper limits to the flux densities of any subparsec-scale radio cores that are at least an order of magnitude lower than the original VLBI radio-core detections, directly challenging the original binary SMBH detection claim. With this in mind, we discuss the possible reasons for the nondetection of any VLBI radio cores in our imaging, the possibility of a binary SMBH still residing in NGC 7674, and the prospect of future observations shedding further light on the true nature of this active galactic nucleus. 

This paper presents the first 28 nm ASIC implementation of an accelerator for the post-quantum digital signature scheme XMSS. In particular, this paper presents an architecture for a novel, pipelined XMSS Leaf accelerator for accelerating the most compute-intensive step in the XMSS algorithm. This paper then presents the ASIC designs for both an existing non-pipelined accelerator architecture and the novel, pipelined XMSS Leaf accelerator. In addition, the performance of the28 nm ASIC is compared to the same designs on 28 nm Artix-7FPGAs. The novel pipelined XMSS Leaf accelerator is 25% faster compared to the non-pipelined version in the ASIC, and both accelerator architectures have a 10×lower power consumption than on the FPGAs. The evaluation shows that the pipelining increases the frequency by 1.7×on the FPGA but only 1.2×on the ASIC, due to the critical path in the ASIC being in the memory. The non-pipelined XMSS Leaf accelerator is shown to have a significantly better area-delay and energy-delay metric on the ASIC, while the pipelined accelerator wins out in these metrics on the FPGA. Consequently, this work shows the different architectural decisions that need to be made between FPGA and ASIC designs, when selecting how to best implement a post-quantum cryptographic accelerator in hardware.