Search for: All records

In order to enable the simultaneous transmission and reception of wireless signals on the same frequency, a fullduplex (FD) radio must be capable of suppressing the powerful self-interference (SI) signal emitted from the transmitter and picked up by the receiver. Critically, a major bottleneck in wideband FD deployments is the need for adaptive SI cancellation (SIC) that would allow the FD wireless system to achieve strong cancellation across different settings with distinct electromagnetic environments. In this work, we evaluate the performance of an adaptive wideband FD radio in three different locations and demonstrate that it achieves strong SIC in every location across different bandwidths. 

This article presents a 32-bit floating-point (FP32) programmable accelerator for solving a wide range of partial differential equations (PDEs) based on numerical integration methods. Compared to prior works that have fixed-point systems and are only applicable to specific types of PDEs, our proposed, integration accelerator for PDEs, named INTIACC, accelerator consists of 16 locally interconnected processing elements (PEs) where each PE is a fully programmable reduced instruction set computer (RISC) processor with an FP32 arithmetic logic unit (FP32 ALU) and a custom-designed instruction set architecture (ISA). These features enable INTIACC to generate solutions with high precision and a wide dynamic range and also allow users to implement different numerical algorithms to perform high-order integration methods and to evaluate nonlinear functions. In addition, we create a novel slow-global-fast-local clocking scheme in which PEs operate asynchronously with each other most of the time. We prototype the INTIACC test chip in 65 nm, with a core area of 0.975 mm2. Running at an average local clock frequency of 570 MHz at 1 V, it offers a single-precision computation throughput of 9.12 GFLOPS. Testing results show that with a similar energy-delay product, INTIACC is up to 40× faster than the prior state-of-the-art PDE solver. 

We present a set of experiments utilizing wideband real-time adaptive full-duplex (FD) radios, demonstrating simultaneous transmission and reception on the same frequency channel. Each FD radio consists of a circulator-based antenna interface, a switched-capacitor delay-line-based configurable Radio-Frequency Integrated Circuit (RFIC) that implements Self-Interference Cancellation (SIC), an FPGA that optimizes the RFIC configuration in under 1.1 sec and can adapt to environmental changes in under 0.3 sec, and a Software-Defined Radio (SDR) transmitting OFDM-like packets. We demonstrate a real-time adaptive FD radio that achieves the SIC necessary to reach the noise floor across a wide bandwidth of 50 MHz. Then, we use two FD radios to create a wireless link and showcase the superior FD throughput. 

We propose a numerical integration accelerator (INTIACC) that speeds up the solution of partial differential equations (PDEs) for scientific computing. In contrast to recent works, INTIACC applies to a variety of PDEs and boundary conditions, has enhanced nonlinear function capability, supports high-order integration algorithms, and uses floating-point arithmetic for orders of magnitude smaller solution error. With all the benefits, our test chip still achieves 40X speed-up over prior accelerators and orders of magnitudes over CPU and GPU based systems.