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Creators/Authors contains: "Zou, Yimin"

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  1. ; ; ; ; ; ; ; ( , 2020 IEEE Symposium on VLSI Circuits (VLSI-Circuits))
    We present a neural interface system-on-chip (NISoC) with 1,024 channels of simultaneous electrical recording and stimulation for high-resolution high-throughput electrophysiology. The 2mm  2mm NISoC in 65nm CMOS integrates a 32  32 array of electrodes vertically coupled to analog front-ends supporting both voltage and current clamping through a programmable interface, ranging over 100dB in voltage and 120dB in current, with 0.82mW power per channel at 5.96mVrms input-referred voltage noise from DC to 12.5kHz signal bandwidth. This includes onchip acquisition with a back-end array of 32 dynamic incremental SAR ADCs for 25Msps 11-ENOB acquisition at 2fJ/level FOM.
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