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The use of high κ dielectrics lowers the operating voltage in organic field-effect transistors (FETs). Polymer ferroelectrics open the path not just for high κ values but allow processing of the dielectric films via electrical poling. Poled ferroelectric dielectrics in p-type organic FETs was seen to improve carrier mobility and reduce leakage current when compared to unpoled devices using the same dielectric. For n-type FETs, solution-processed ZnO films provide a viable low-cost option. UV–ozone-treated ZnO films was seen to improve the FET performance due to the filling of oxygen vacancies. P-type FETs were fabricated using the ferroelectric polymer poly(vinylidene fluoride-trifluoroethylene) (PVDF-TrFE) as the dielectric along with a donor–acceptor polymer based on diketopyrrolopyrrole (DPP-DTT) as the semiconductor layer. The DPP-DTT FETs yield carrier mobilities upwards of 0.4 cm2/Vs and high on/off ratios when the PVDF-TrFE layer is electrically poled. For n-type FETs, UV–ozone-treated sol–gel ZnO films on SiO2 yield carrier mobilities of 10−2 cm2/Vs. DPP-DTT-based p- and ZnO-based n-type FETs were used in a complementary voltage inverter circuit, showing promising characteristic gain. A basic inverter model was used to simulate the inverter characteristics, using parameters from the individual FET characteristics. 

Polymer ferroelectrics are playing an increasingly active role in flexible memory application and wearable electronics. The relaxor ferroelectric dielectric, poly(vinylidene fluoride trifluorethylene (PVDF‐TrFE), although vastly used in organic field‐effect transistors (FETs), has issues with gate leakage current especially when the film thickness is below 500 nm. This work demonstrates a novel method of selective poling the dielectric layer. By using solution‐processed 6,13‐bis(triisopropylsilylethynyl)pentacene (TIPS‐pentacene) as the organic semiconductor, it is shown that textured poling of the PVDF‐TrFE layer dramatically improves FET properties compared to unpoled or uniformly poled ferroelectric films. The texturing is achieved by first vertically poling the PVDF‐TrFE film and then laterally poling the dielectric layer close to the gate electrode. TIPS‐pentacene FETs show on/off ratios of 10⁵and hole mobilities of 1 cm²Vs⁻¹under ambient conditions with operating voltages well below −5 V. The electric field distribution in the dielectric layer is simulated by using finite difference time domain methods.