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While negative capacitance (NC) has been demonstrated in ferroelectric-dielectric (FE-DE) heterostructures in the form of capacitance enhancement, all experimental evidence, to date, suggests the existence of domains therein. Here, we address the question: what are the conditions to achieve ideal, domain-free NC in FE-DE heterostructures? Our main claim is that for given thicknesses of the ferroelectric and the dielectric layers, there is a critical value of domain wall energy parameter— above which the system would be stabilized in an ideal and robust domain-free NC state and would be robust against domain formation. Our analyses suggest that to achieve ideal NC, efforts should lie in understanding the means to control the domain wall energy on all fronts, both theory and experiments via high throughput design, discovery, and engineering of ferroelectrics.
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null (Ed.)Doped HfO2 based ferroelectric FET (FeFET) exhibits a greatly improved retention performance compared with its perovskite counterpart due to its large coercive field, which prevents domain flip during retention. In this work, however, through extensive temperature dependent experimental characterization and modeling, we are demonstrating that: 1) with FeFET geometry scaling, the polarization states are no longer stable, but exhibit multi-step degradation and cause reduced sense margin in distinguishable adjacent levels or even eventual memory window collapse; 2) the instability is caused by the temperature activated accumulation of switching probability under depolarization field stress, which could cause domain switching within the retention time at operating temperatures.more » « less
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This paper presents a Ferroelectric FET (FeFET) based processing-in-memory (PIM) architecture to accelerate inference of deep neural networks (DNNs). We propose a digital in-memory vector-matrix multiplication (VMM) engine design utilizing the FeFET crossbar to enables bit-parallel computation and eliminate analog-to-digital conversion in prior mixed-signal PIM designs. A dedicated hierarchical network-on-chip (H-NoC) is developed for input broadcasting and on-the-fly partial results processing, reducing the data transmission volume and latency. Simulations in 28nm CMOS technology show 115x and 6.3x higher computing efficiency (GOPs/W) over desktop GPU (Nvidia GTX 1080Ti) and ReRAM based design, respectively.more » « less
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