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A Dual-Channel High-Linearity Filtering-by-Aliasing Receiver Front-End Supporting Carrier Aggregation

https://doi.org/10.1109/JSSC.2021.3112183

Bu, Shi; Pamarti, Sudhakar (May 2022, IEEE Journal of Solid-State Circuits)

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A Digital Alias Cancellation Technique for Filtering-by-Aliasing Receivers

Shi Bu, Sudhakar Pamarti (January 2022, International Symposium on Circuits and Systems Proceedings)

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Periodically Time-Varying Noise Cancellation for Filtering-by-Aliasing Receiver Front Ends

https://doi.org/10.1109/JSSC.2020.3028357

Bu, Shi; Hameed, Sameed; Pamarti, Sudhakar (March 2021, IEEE Journal of Solid-State Circuits)
null (Ed.)
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6.3 A 0.9V Dual-Channel Filtering-by-Aliasing Receiver Front-End Achieving +35dBm IIP ₃ and <-81dBm LO Leakage Supporting Intra-and Inter-Band Carrier Aggregation

https://doi.org/10.1109/ISSCC42613.2021.9366017

Bu, Shi; Pamarti, Sudhakar (February 2021, 2021 IEEE International Solid State Circuits Conference)
null (Ed.)
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An LPTV Noise Cancellation Technique for a 0.9-V Filtering-by-Aliasing Receiver Front-End with >67-dB Stopband Rejection

https://doi.org/10.1109/CICC.2019.8780315

Bu, Shi; Hameed, Sameed; Pamarti, Sudhakar (April 2019, 2019 IEEE Custom Integrated Circuits Conference)

A linear periodically time-varying (LPTV) noise cancellation technique for filtering-by-aliasing (FA) receivers is presented in this paper. Fabricated in a 28-nm CMOS process, it improves the noise Figure (NF) by about 3 dB while achieving over 67-dB stopband rejection with a transition bandwidth of only four times the RF BW. A minimum in-band NF of 3.2 dB is demonstrated. With an upfront -path filter to further enhance the linearity, the measured out-of-band IIP 3 is + 18 dBm and the blocker 1-dB compression point is + 9 dBm. Operating under a 0.9V supply, it consumes 61-mW power at 500-MHz LO.
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