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Abstract Despite superconductor electronics (SCE) advantages, the realization of SCE logic faces a significant challenge due to the absence of dense and scalable nonvolatile memory. While various nonvolatile memory technologies, including Non-destructive readout, vortex transitional memory, and magnetic memory, have been explored, designing a dense crossbar array and achieving a superconductor random-access memory remains challenging. This work introduces a novel, nonvolatile, high-density, and scalable vortex-based memory design for SCE logic called bistable vortex memory. Our proposed design addresses scaling issues with an estimated area of 10 × 10 um²while boasting zero static power with the dynamic energy consumption of 12 aJ for single-bit read and write operations. The current summation capability enables analog operations for in-memory or near-memory computational tasks. We demonstrate the efficacy of our approach with a 32 × 32 superconductor memory array operating at 20 GHz. Additionally, we showcase the accumulation property of the memory through analog simulations conducted on an 8 × 8 superconductor crossbar array. 

Abstract A novel high-fan-in differential superconductor neuron structure designed for ultra-high-performance spiking neural network (SNN) accelerators is presented. Utilizing a high-fan-in neuron structure allows us to design SNN accelerators with more synaptic connections, enhancing the overall network capabilities. The proposed neuron design is based on superconductor electronics fabric, incorporating multiple superconducting loops, each with two Josephson Junctions. This arrangement enables each input data branch to have positive and negative inductive coupling, supporting excitatory and inhibitory synaptic data. Compatibility with synaptic devices and thresholding operation is achieved using a single flux quantum pulse-based logic style. The neuron design, along with ternary synaptic connections, forms the foundation for a superconductor-based SNN inference. To demonstrate the capabilities of our design, we train the SNN using snnTorch, augmenting the PyTorch framework. After pruning, the demonstrated SNN inference achieves an impressive 96.1% accuracy on MNIST images. Notably, the network exhibits a remarkable throughput of 8.92 GHz while consuming only 1.5 nJ per inference, including the energy consumption associated with cooling to 4 K. These results underscore the potential of superconductor electronics in developing high-performance and ultra-energy-efficient neural network accelerator architectures. 

Abstract Josephson-CMOS hybrid memory leverages the high speed and low power operation of single-flux quantum logic and the high integration densities of CMOS technology. One of the commonly used type of interface circuits in Josephson-CMOS memory is a Suzuki stack, which is a latching high-voltage driver circuit. Suzuki stack circuits are typically powered by an AC bias voltage that has several limitations such as synchronization and coupling effects. To address these issues, a novel DC-biased Suzuki stack circuit is proposed in this paper. As compared to a conventional AC-biased Suzuki stack circuit, the proposed DC-biased design can provide similar output voltage levels and parameter margins, approximately two times higher operating frequency, and three orders of magnitude lower heat load of bias cables. 

Abstract Superconductor Electronics (SCE) is a fast and power-efficient technology with great potential for overcoming conventional CMOS electronics' scaling limits. Nevertheless, the primary challenge confronting SCE today is its integration level, which lags several orders of magnitude behind CMOS circuits. In this study, we have innovated and simulated a novel logic family grounded in the principles of phase shifts occurring in 0 and π Josephson junctions. The fast phase logic (FPL) eliminates the need for large inductor loops and shunt resistances by combining the half-flux and phase logic. Therefore, the Josephson junction (JJ) area only limits the integration density. The cells designed with this paradigm are fast, and the clock-to-Q delay for logic cells is about 4ps. While maintaining over 50% parameter margins for wiring cells. This logic is power efficient and can increase the integration by at least 100 times in the SCE chips.