Search for: All records

Summary Digital MemComputing machines (DMMs), which employ nonlinear dynamical systems with memory (time non‐locality), have proven to be a robust and scalable unconventional computing approach for solving a wide variety of combinatorial optimization problems. However, most of the research so far has focused on the numerical simulations of the equations of motion of DMMs. This inevitably subjects time to discretization, which brings its own (numerical) issues that would be otherwise absent in actual physical systems operating in continuous time. Although hardware realizations of DMMs have been previously suggested, their implementation would require materials and devices that are not so easy to integrate with traditional electronics. Addressing this, our study introduces a novel hardware design for DMMs, utilizing readily available electronic components. This approach not only significantly boosts computational speed compared to current models but also exhibits remarkable robustness against additive noise. Crucially, it circumvents the limitations imposed by numerical noise, ensuring enhanced stability and reliability during extended operations. This paves a new path for tackling increasingly complex problems, leveraging the inherent advantages of DMMs in a more practical and accessible framework. 

Abstract Neuromorphic systems are typically based on nanoscale electronic devices, but nature relies on ions for energy-efficient information processing. Nanofluidic memristive devices could thus potentially be used to construct electrolytic computers that mimic the brain down to its basic principles of operation. Here we report a nanofluidic device that is designed for circuit-scale in-memory processing. The device, which is fabricated using a scalable process, combines single-digit nanometric confinement and large entrance asymmetry and operates on the second timescale with a conductance ratio in the range of 9 to 60. In operando optical microscopy shows that the memory capabilities are due to the reversible formation of liquid blisters that modulate the conductance of the device. We use these mechano–ionic memristive switches to assemble logic circuits composed of two interactive devices and an ohmic resistor. 

Abstract In the ‘Beyond Moore’s Law’ era, with increasing edge intelligence, domain-specific computing embracing unconventional approaches will become increasingly prevalent. At the same time, adopting a variety of nanotechnologies will offer benefits in energy cost, computational speed, reduced footprint, cyber resilience, and processing power. The time is ripe for a roadmap for unconventional computing with nanotechnologies to guide future research, and this collection aims to fill that need. The authors provide a comprehensive roadmap for neuromorphic computing using electron spins, memristive devices, two-dimensional nanomaterials, nanomagnets, and various dynamical systems. They also address other paradigms such as Ising machines, Bayesian inference engines, probabilistic computing with p-bits, processing in memory, quantum memories and algorithms, computing with skyrmions and spin waves, and brain-inspired computing for incremental learning and problem-solving in severely resource-constrained environments. These approaches have advantages over traditional Boolean computing based on von Neumann architecture. As the computational requirements for artificial intelligence grow 50 times faster than Moore’s Law for electronics, more unconventional approaches to computing and signal processing will appear on the horizon, and this roadmap will help identify future needs and challenges. In a very fertile field, experts in the field aim to present some of the dominant and most promising technologies for unconventional computing that will be around for some time to come. Within a holistic approach, the goal is to provide pathways for solidifying the field and guiding future impactful discoveries. 

We present a fully parallel digital memcomputing solver implemented on a field-programmable gate array (FPGA) board. For this purpose, we have designed an FPGA code that solves the ordinary differential equations associated with digital memcomputing in parallel. A feature of the code is the use of only integer-type variables and integer constants to enhance optimization. Consequently, each integration step in our solver is executed in 96 ns. This method was utilized for difficult instances of the Boolean satisfiability (SAT) problem close to a phase transition, involving up to about 150 variables. Our results demonstrate that the parallel implementation reduces the scaling exponent by about 1 compared to a sequential C++ code on a standard computer. Additionally, compared to C++ code, we observed a time-to-solution advantage of about three orders of magnitude. Given the limitations of FPGA resources, the current implementation of digital memcomputing will be especially useful for solving compact but challenging problems. 

Memcomputing logic gates generalize the traditional Boolean logic gates for operation in the reverse direction. According to the literature, this functionality enables efficient solution of computationally intensive problems, including factorization and NP-complete problems. To approach the deployment of memcomputing gates in hardware, this paper introduces SPICE models of memcomputing logic gates following their original definition. Using these models, we demonstrate the behavior of single gates as well as small self-organizing circuits. We have also corrected some inconsistencies in the prior literature. Notably, the correct schematics of the dynamic correction module is reported here for the first time. Our work makes memcomputing more accessible to those interested in this emerging computing technology. 

Memcomputing is a novel computing paradigm beyond the von–Neumann one. Its digital version is designed for the efficient solution of combinatorial optimization problems, which emerge in various fields of science and technology. Previously, the performance of digital memcomputing machines (DMMs) was demonstrated using software simulations of their ordinary differential equations. Here, we present the first hardware realization of a DMM algorithm on a low-cost FPGA board. In this demonstration, we have implemented a Boolean satisfiability problem solver. To optimize the use of hardware resources, the algorithm was partially parallelized. The scalability of the present implementation is explored and our FPGA-based results are compared to those obtained using a python code running on a traditional (von–Neumann) computer, showing one to two orders of magnitude speed-up in time to solution. This initial small-scale implementation is projected to state-of-the-art FPGA boards anticipating further advantages of the hardware realization of DMMs over their software emulation. 

MemComputing is a new model of computation that exploits the non-equilibrium property—we call “memory”—of any physical system to respond to external perturbations by keeping track of how it has reacted at previous times. Its digital, scalable version maps a finite string of symbols into a finite string of symbols. In this paper, I will discuss some analogies of the operation of MemComputing machines—in general, and digital in particular—with a few physical properties of the biological brain. These analogies could be a source of inspiration to improve on the design of these machines. In turn, they could suggest new directions of study in (computational) neuroscience.